Hardware Description Language Implementation Research Articles

A Hardware Descriptive Approach to Beetle Antennae Search

Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms. The common practice for implementing meta-heuristic algorithms including the BAS largely relies on programming in a high-level language and executing the code on a computer platform. However, the high-level implementation of the BAS algorithm hinders it from being used in an embedding system, where real-time operations are normally required. To address this limitation, we present an approach to implementing the BAS algorithm on a field-programmable gate array (FPGA). Specifically, we program the BAS function in the Verilog hardware description language (HDL), which provides a tractable vehicle for implementing the BAS algorithm at the gate level on the FPGA chip. We simulate our Verilog HDL based BAS module with the Modelsim platform. Simulation results validate the feasibility of our proposed Verilog HDL implementation of the BAS. Additionally, we implement the BAS model on the Zynq XC7Z010 platform, with $132.5~\mu $ s latency for model implementation.

Automated State Machine and Timing Characteristic Extraction for RSFQ Circuits

We present a heuristic for the automated extraction of state machine representations of rapid single-flux-quantum (RSFQ) digital logic circuits given a circuit SPICE representation. Furthermore, this heuristic uses the SPICE netlist to extract timing characteristics for the creation of a hardware description language (HDL) implementation of the circuit. This facilitates RSFQ logic design at an HDL level rather than a Josephson junction level. The state machine extraction method can be also used for the automatic creation of test benches for circuit yield analysis, as well as optimization algorithms. An example of the automatic extraction of the state machine representation, timing characterization, and HDL implementation is demonstrated for a complex RSFQ cell.

Vehicle State and Friction Force Estimation Based on FPGA

In order to improve the computational performance of the nonlinear observer for vehicle state and friction force estimation, two novel implementation schemes in Verilog Hardware Description Language (HDL) and System on Programmable Chip (SoPC) is proposed based on Field Programmable Gate Array (FPGA). Firstly, the parallelism analysis of the vehicle state and friction force estimation algorithm is provided. Then, the Verilog HDL and SoPC implementation schemes are presented respectively based on the analysis results. Finally, a testing platform is built to evaluate the functionality and the computational performance of the implementation schemes. The experimental results show that the proposed schemes all have high precision and computational efficiency for vehicle state and friction force estimation.

A formal HDL and its use in the FM9001 verification

A synchronous, hierarchical, occurrence-oriented, hardware description language (HDL) has been formalized with the Boyer-Moore logic. Well-formed HDL circuits are recognized by a predicate, and a unit-clock simulator defines the meaning of circuits expressed in the HDL. This HDL has been used to specify an implementation of the FM9001 microprocessor that has been mechanically proved to implement the FM9001 instruction-level specification. All proofs were mechanically checked using the Boyer-Moore theorem-proving system. The formalization of the HDL, the FM9001 user-level specification, and the FM9001 HDL implementation architecture specification required more than 700 function definitions. The mechanical proof is composed of thousands of theorem prover proof requests and millions of theorem prover inference steps.