Abstract
Beetle antennae search (BAS) is a newly developed meta-heuristic algorithm which is effectively used for optimizing objective functions of complex forms or even unknown forms. The common practice for implementing meta-heuristic algorithms including the BAS largely relies on programming in a high-level language and executing the code on a computer platform. However, the high-level implementation of the BAS algorithm hinders it from being used in an embedding system, where real-time operations are normally required. To address this limitation, we present an approach to implementing the BAS algorithm on a field-programmable gate array (FPGA). Specifically, we program the BAS function in the Verilog hardware description language (HDL), which provides a tractable vehicle for implementing the BAS algorithm at the gate level on the FPGA chip. We simulate our Verilog HDL based BAS module with the Modelsim platform. Simulation results validate the feasibility of our proposed Verilog HDL implementation of the BAS. Additionally, we implement the BAS model on the Zynq XC7Z010 platform, with $132.5~\mu $ s latency for model implementation.
Highlights
A large number of meta-heuristic algorithms are designed by simulating certain biological behaviors
In order to explore the possibility of operating the beetle antennae search (BAS) at a circuit level rather than programming it in a highlevel language, we investigate the scheme of implementing the BAS on an field-programmable gate array (FPGA)
VERILOG hardware description language (HDL) IMPLEMENTATION OF BAS we introduce the approach to implementing BAS by Verilog HDL
Summary
A large number of meta-heuristic algorithms are designed by simulating certain biological behaviors. The implementations of meta-heuristic algorithms (e.g., the BAS) largely rely on programming in a high-level language and executing the code on a computer platform. The high-level implementation of the BAS algorithm hinders it from being used in an embedding system, where real-time operations are normally required. The main contributions of our work are summarized as follows: 1) We are the first first to present an approach that implements the BAS algorithm on FPGA. We develop a twin model of LFSR along with a fixed-point arithmetic scheme, resulting a unique implementation approach to the BAS on the FPGA platform Zynq XC7Z010. The BAS algorithm is formulated in terms of repeating the cycle of directional flying and randomly directional landing until the optimal value of f (x) is obtained. The equation (1) is used for characterizing the orientation of an antenna randomly placed by the beetle
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.