Hardware-based Schemes Research Articles

Cyberattack Defense With Cyber-Physical Alert and Control Logic in Industrial Controllers

Power system substations have intelligent electronic devices (IEDs) that collect data and control other devices. As the bridge between the physical and cyber parts of the power system, IEDs capture some key system behaviors. Since adversaries can modify the system’s behavior, physical and cyber data can be used to infer characteristics about the adversary. In this article, we present alert and control logic for hardware-based power system defense using the physical data and communication status in substation IEDs for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cyber threat detection</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cyber-physical contingency detection and response</i> , and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">physical contingency identification and response</i> . The proposed alert and control logic routines are implemented in an industrial real-time automation controller using IEC 61131-3 in the resilient energy systems lab testbed. The goal is to help operators identify adversaries and protect the power grid in a cyber-physical environment. The effectiveness and accuracy of logic schemes are validated under different adversarial scenarios. Comparing the proposed schemes with an intrusion detection system, Snort, our results also suggest the benefits of using cyber and physical data to identify threats. The results also suggest the use of such hardware-based schemes with software algorithms in a next-generation cyber-physical energy management system, which can implement automatic control actions to protect power grids and its physical equipment against cyber threats.

Modern Authentication Schemes in Smartphones and IoT Devices: An Empirical Survey

User authentication remains a challenging issue, despite the existence of a large number of proposed solutions, such as traditional text-based, graphical-based, biometrics-based, Web-based, and hardware-based schemes. For example, some of these schemes are not suitable for deployment in an Internet of Things (IoT) setting, partly due to the hardware and/or software constraints of IoT devices. The increasing popularity and pervasiveness of IoT equipment in a broad range of settings reinforces the importance of ensuring the security and privacy of IoT devices. Therefore, in this article, we conduct a comprehensive literature review and an empirical study to gain an in-depth understanding of the different authentication schemes as well as their vulnerabilities and deficits against various types of cyberattacks when applied in IoT-based systems. Based on the identified limitations, we recommend several mitigation strategies and discuss the practical implications of our findings.

Evaluation and defense of light commands attacks against voice controllable systems in smart cars

The in-car voice controllable system has become an almost standard feature in smart cars. Prior work shows that the voice controllable system is vulnerable to light commands attack which uses the laser as the medium to inject voice commands. In this article, we first reproduced the light commands attack on acoustic isolated in-car voice controllable system under several scenarios with a lightweight solution. We validate the feasibility of injecting the malicious voice command through a window into the microphone by modulating a laser beam. Then, we tested a variety of mainstream countermeasures such as placing sunscreen film on the glass panel to see whether it can protect the microphone from being attacked. Surprisingly, we find that the lower light transmittance of sunscreen film is the lower the success rate of the attack. Experiment results also show that when the transmittance rate of sun film is 50% which is the darkest sunscreen film that can be applied, the attacking success rate decreased by up to 0.4. We also explore the impact of attack angle by changing the incidence angle of the laser beam and the results demonstrate that light commands is sensitive to attack angle and the successful angle range is ± 15°. Finally, we propose a series of hardware-based protection schemes against light commands attacks.

An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment

Biological sequence alignment procedure demands an accurate, high speed, and efficient system to align sequences due to exponential growth of genomic databases. Several software-based as well as hardware-based schemes have been developed to perform alignment operation. Unfortunately, these approaches do not meet the requirement of hardware resource and processing time of recent growth of biological sequences. This article presents a pipelined-multiprocessor architecture with an energy-efficient approach to meet the requirement of processing of alignment operation at hardware speed. This architecture introduces register-file concept, instead of conventional memory-based approach, to reduce run-time storage requirement as well as power consumption. In addition, the proposed alignment architecture does not incur any preprocessing operations present in most of the existing alignment approaches. Moreover, it does not need any sorting or comparison operation during the preparation of final sequence alignment. This architecture achieves 128 GCUPS performance and also acquires 107.20 GCUPS/W throughput with respect to power consumption. The proposed architecture brings down 97.29% power consumption compared to state of the art multiprocessor architectures. Experimentally, it has been observed that, this novel architecture exhibits reduction in energy consumption by ≈97.51% and achieves 2.56 GCUPS gain factor in an energy-efficient manner over all existing hardware approaches.

Analytic Model for Optimal Checkpoints in Mobile Real-time Systems

It is not practically feasible to apply hardware-based fault-tolerant schemes, such as hardware replication, in mobile devices. Therefore, software-based fault-tolerance techniques, such as checkpoint and rollback schemes, are required. In checkpoint and rollback schemes, the optimal checkpoint interval should be applied to obtain the best performance. Most previous studies focused on minimizing the expected execution time or response time for completing a given task. Currently, most mobile applications run in real-time environments. Therefore, it is extremely essential for mobile devices to employ optimal checkpoint intervals as determined by the real-time constraints of tasks. In this study, we tackle the problem of determining the optimal inter-checkpoint interval of checkpoint and rollback schemes to maximize the deadline meet ratio in real-time systems and to build a probabilistic cost model. From this cost model, we can numerically find the optimal checkpoint interval using mathematical tools. The performance of the proposed solution is evaluated using analytical estimates.

Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline

Miniaturization of very large scale integration circuits, higher frequencies and reduction of supply voltages make embedded systems more susceptible to soft errors (or transient errors). Soft errors affect the processor's pipeline and hence its data and control flows. Specifically, errors in control flows can change program's execution sequence, which might be catastrophic for safety-critical applications. Several state-of-the-art techniques are available for control flow error checking (CFEC). Software-based techniques suffer from increased code size overhead and can have a negative impact on energy consumption. On the other hand, hardware-based schemes incur high hardware and area costs. In this paper, a low-cost CFEC scheme is proposed that exploits available redundancies in the processor's pipeline; a branch target buffer stores the target addresses of taken branches, a short backward branch detector stores short loop branch targets and an arithmetic logic unit generates branch target addresses using the low-order branch displacement bits of branch instructions. The proposed CFEC scheme uses these redundancies to detect and recover from control flow errors in the pipeline with low energy overhead of 0.9% and performance overhead of 0.8%, while its error coverage ranges from 86% to 99%.

Exploring the limits of early register release

Register pressure in modern superscalar processors can be reduced by releasing registers early and by copying their contents to cheap back-up storage. This article quantifies the potential benefits of register occupancy reduction and shows that existing hardware-based schemes typically achieve only a small fraction of this potential. This is because they are unable to accurately determine the last use of a register and must wait until the redefining instruction enters the pipeline. On the other hand, compilers have a global view of the program and, using simple dataflow analysis, can determine the last use. This article evaluates the extent to which compiler analysis can aid early releasing, explores the design space, and introduces commit and issue-based early releasing schemes, quantifying their benefits. Using simple compiler analysis and microarchitecture changes, we achieve 70% of the potential register file occupancy reduction. By adding more hardware support, we can increase this to 94%. Our schemes are compared to state-of-the-art approaches for varying register file sizes and are shown to outperform these existing techniques.

Capo

While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on multiprocessors, while hardware-based proposals focus only on basic hardware-level mechanisms, ignoring the overall replay system. To be practical, hardware-based replay systems need to support an environment with multiple parallel jobs running concurrently -- some being recorded, others being replayed and even others running without recording or replay. Moreover, they need to manage limited-size log buffers. This paper addresses these shortcomings by introducing, for the first time, a set of abstractions and a software-hardware interface for practical hardware-assisted replay of multiprocessor systems. The approach, called Capo , introduces the novel abstraction of the Replay Sphere to separate the responsibilities of the hardware and software components of the replay system. In this paper, we also design and build CapoOne , a prototype of a deterministic multiprocessor replay system that implements Capo using Linux and simulated DeLorean hardware. Our evaluation of 4-processor executions shows that CapoOne largely records with the efficiency of hardware-based schemes and the flexibility of software-based schemes.

Capo

While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on multiprocessors, while hardware-based proposals focus only on basic hardware-level mechanisms, ignoring the overall replay system. To be practical, hardware-based replay systems need to support an environment with multiple parallel jobs running concurrently -- some being recorded, others being replayed and even others running without recording or replay. Moreover, they need to manage limited-size log buffers. This paper addresses these shortcomings by introducing, for the first time, a set of abstractions and a software-hardware interface for practical hardware-assisted replay of multiprocessor systems. The approach, called Capo , introduces the novel abstraction of the Replay Sphere to separate the responsibilities of the hardware and software components of the replay system. In this paper, we also design and build CapoOne , a prototype of a deterministic multiprocessor replay system that implements Capo using Linux and simulated DeLorean hardware. Our evaluation of 4-processor executions shows that CapoOne largely records with the efficiency of hardware-based schemes and the flexibility of software-based schemes.

Thread partitioning and value prediction for exploiting speculative thread-level parallelism

Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model strongly depends on the performance of the control and data speculation techniques. Several hardware-based schemes for partitioning the program into speculative threads are analyzed and evaluated. In general, we find that spawning threads associated to loop iterations is the most effective technique. We also show that value prediction is critical for the performance of all of the spawning policies. Thus, a new value predictor, the increment predictor, is proposed. This predictor is specially oriented for this kind of architecture and clearly outperforms the adapted versions of conventional value predictors such as the last value, the stride, and the context-based, especially for small-sized history tables.

Efficient use of memory bandwidth to improve network processor throughput

We consider the efficiency of packet buffers used in packet switches built using network processors (NPs). Packet buffers are typically implemented using DRAM, which provides plentiful buffering at a reasonable cost. The problem we address is that a typical NP workload may be unable to utilize the peak DRAM bandwidth. Since the bandwidth of the packet buffer is often the bottleneck in the performance of a shared-memory packet switch, inefficient use of available DRAM bandwidth further reduces the packet throughput. Specialized hardware-based schemes that alleviate the DRAM bandwith problem in high-end routers may be less applicable to NP-based systems, in which cost is an important consideration.In this paper, we propose cost-effective ways to enhance average-case DRAM bandwidth. In modern DRAMs, successive accesses falling within the same DRAM row are significantly faster than those falling across rows. If accesses to DRAM can be generated differently or reordered to take advantage of fast same-row accesses, peak DRAM bandwidth can be approached. The challenge is in exploiting this "row locality" despite the unpredictable nature of memory accesses in NPs. We propose a set of simple techniques to meet this challenge. These include locality-sensitive buffer allocation on packet input, reordering DRAM accesses to increase locality, and prefetching to reduce row miss penalty. We evaluate our techniques on cycle-accurate simulations of Intel's IXP 1200 network processor and find that they boost packet throughput on average by 42.7%, utilizing nearly the peak DRAM bandwidth, for a set of common NP applications processing a real trace.

A new adaptive hardware tree-based multicast routing in k-ary n-cubes

Multicast communication is a key issue in almost all applications that run on any parallel architecture and, hence, efficient implementation of multicast is critical to the performance of multiprocessor machines. Multicast is implemented in parallel architectures either via software or via hardware. Software-based approaches for implementing multicast can result in high message latencies, while hardware-based schemes can greatly improve performance. Deadlock freedom in multicast communication is much more difficult to achieve resulting in more involved routing algorithms and higher startup delays. Hardware tree-based algorithms do not require these high startup delays, but do suffer from high probabilities of message blocking leading to poor performance. In this paper, we propose a new hardware tree-based routing algorithm (HTA) for multicast communication under virtual cut-through switching in k-ary n-cubes that outperforms existing software and hardware path-based multicast routing schemes. Simulation results are compared against several commonly used multicast routing algorithms and show that HTA performs extremely well under many different conditions.