Hardware Algorithms Research Articles

Implementation of an on-line adaptive fuzzy controller in low-end hardware

The implementation of an on-line adaptive fuzzy control algorithm in low-end hardware is described. The adaptive controller starts with a vacuous control policy, i.e. its initial control surface is derived from a vacuous rule base. The control surface is adapted autonomously in real time using control meta-knowledge and basic learning constructs. Limited system-dependent information is incorporated to tailor the Intel-8031-based hardware to specific applications. This information includes input and output signal magnitudes and time-scale information. Simulations and actual experiments indicate that the on-line adaptive controller is very robust and fault-tolerant. A relatively high learning rate enables the controller to learn to control plants in real time even while it is controlling them.

VLSI ARCHITECTURES FOR PATTERN MATCHING

The recognition of patterns is an important task in robot and computer vision. The patterns themselves could be one- or two-dimensional, depending upon the application. Pattern matching is a computationally intensive and time consuming operation. The design of special purpose hardware could speed up the matching task considerably, making real-time responses possible. Advances in parallel processing and VLSI technologies have made it possible to implement inexpensive, efficient and very fast custom designs. Many approaches and solutions have been proposed in the literature for hardware implementations of pattern matching techniques. In this paper, we present a detailed overview of some of the important contributions in the area of hardware algorithms and architectures for pattern matching.

BKM: a new hardware algorithm for complex elementary functions

A new algorithm for computing the complex logarithm and exponential functions is proposed. This algorithm is based on shift-and-add elementary steps, and it generalizes some algorithms by Briggs and De Lugish (1970), as well as the CORDIC algorithm. It can easily be used to compute the classical real elementary functions (sin, cos, arctan, ln, exp). This algorithm is more suitable for computations in a redundant number system than the CORDIC algorithm, since there is no scaling factor when computing trigonometric functions. >

Analysis of noncoherent systems and an architecture for the computation of the system reliability

An efficient technique for computing the reliability of k-to-l-out-of-n systems is presented. These kinds of systems find application in communication, multiprocessor, and transportation system environments. The k-to-l-out-of-n systems are very general and readily model coherent systems such as series, parallel, and N-modular-redundancy (NMR) systems. The algorithm presented computes in quadratic time in the worst case and yields superior results compared to existing algorithms for all permissible values of k, l, and n. The scheme is shown to evaluate the reliability in linear order-time. A cellular implementation of the algorithm in hardware is presented. The basic cell consists of a simple multiplier, an adder, and some switches that can be easily implemented in VLSI using computer-aided-design (CAD) tools. Ways of obtaining optimal configurations for the k-to-l-out-of-n system are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Terminal repeller unconstrained subenergy tunneling (trust) for fast global optimization

A new method for unconstrained global function optimization, acronymedtrust, is introduced. This method formulates optimization as the solution of a deterministic dynamical system incorporating terminal repellers and a novel subenergy tunneling function. Benchmark tests comparing this method to other global optimization procedures are presented, and thetrust algorithm is shown to be substantially faster. Thetrust formulation leads to a simple stopping criterion. In addition, the structure of the equations enables an implementation of the algorithm in analog VLSI hardware, in the vein of artificial neural networks, for further substantial speed enhancement.

WEATHER FORECASTING AND PARALLEL PROCESSING: A VIEW FROM ECMWF

Operational numerical weather prediction requires that all available main-frame computing power be harnessed to the one task, in order to maintain operational schedules. ECMWF therefore became involved in parallel processing as soon as it became available on supercomputers. The main operational programs were restructured to use multitasking on a limited number of processors, currently 8. The availability of supercomputers with massively parallel architecture which is expected in the near future raises quite a number of major problems. These areas have been discussed in the biennial workshops held at ECMWF since 1984. Besides the user environment, the inter-dependency of hardware architecture and algorithms needs most attention. To study these questions, ECMWF became involved in the GENESIS project sponsored by the European Community. Initial results of this co-operation in the form of benchmark results will be presented. The challenges posed by new developments in weather prediction strategies will be highlighted and an assessment of the impact parallel computing will have on their being met will be made.

A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits

It is shown how to represent the objective function of the memory repair problem as a neural-network energy function, and how to exploit the neural network's convergence property for deriving optimal repair solutions. Two algorithms have been developed using a neural network, and their performances are compared with that of the repair most (RM) algorithm. For randomly generated defect patterns, a proposed algorithm with a hill-climbing capability successfully repaired memory arrays in 98% cases, as opposed to RMs 20% cases. It is demonstrated how, by using very small silicon overhead, one can implement this algorithm in hardware within a VLSI chip for built in self repair (BISR) of memory arrays. The proposed auto-repair approach is shown to improve the VLSI chip yield by a significant factor, and it can also improve the life span of the chip by automatically restructuring its memory arrays in the event of sporadic cell failures during the field use.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-speed VLSI designs for Lempel-Ziv-based data compression

A class of hardware algorithms for implementing the Lempel-Ziv-based data compression technique is described. The Lempel-Ziv-based compression method is a powerful technique for lossless data compression that gives high compression efficiency for text as well as image data. The proposed hardware algorithms exploit the principles of pipelining and parallelism in order to obtain high speed and throughput. A prototype CMOS VLSI chip was designed and fabricated using 2- mu m CMOS technology implementing a systolic array of nine processors. The chip gives a compression rate of 13.3 MB/s operating at 40 MHz. Two hardware algorithms for the decompression process are also described. The data compression hardware can be integrated into real-time systems so that data can be compressed and decompressed on-the-fly. >

Target detection by co-occurrence matrix segmentation and its hardware implementation

A number of acquisition, tracking, and classification algorithms have been developed to deal with various image processing problems in the laboratory. Typically, these algorithms are too complicated to implement in a low-cost, real-time processor. Using image data in many real-time applications requires a system with very high data rates, low power dissipation, and a small packaging volume. We developed a processor architecture suitable for these applications, and adapted and demonstrated a co-occurrence matrix target detection algorithm in computer simulation and real-time hardware. A histogram, or gray-level distribution, is often used to select a threshold for image segmentation. This technique is often inadequate because the histograms tend to be noisy and exhibit many small peaks. Co-occurrence matrix-based segmentation allows homogeneous regions of an image to be identified and separated from a cluttered background. Results are shown for target segmentation using representative infrared imagery and real-time hardware.

Density Functional Methods and Applications to Materials Problems

AbstractDensity functional theory provides a first-principles approach for computing the geometric and electronic structures, and a wealth of corresponding properties, of a wide range of materials types and compositions, including bulk solids, surfaces, defects and clusters of molecules. Parallel advances in hardware performance, implementation strategies and algorithms have all contributed to a rapid growth in the number of important applications. Recent developments under each of these themes are outlined and the breadth of current applications is illustrated by typical examples. Issues associated with the implementation and performance of density functional methods on parallel computer architectures are discussed.

CLUSTER ALGORITHM SPECIAL PURPOSE PROCESSOR

We describe a Special Purpose Processor, realizing the Wolff algorithm in hardware, which is fast enough to study the critical behaviour of 2D Ising-like systems containing more than one million spins. The processor has been checked to produce correct results for a pure Ising model and for Ising model with random bonds. Its data also agree with the Nishimori exact results for spin glass. Only minor changes of the SPP design are necessary to increase the dimensionality and to take into account more complex systems such as Potts models.

Earth observing SAR data processing systems at the Jet Propulsion Laboratory — SEASAT to EOS SAR

This paper traces the evolution of SAR digital data processing and management systems developed at JPL for earth science missions. The Interim Digital Processor (IDP) was developed for SEASAT SAR, utilizing a general-purpose mini-computer and commercial array processors. The IDP established the fundamental algorithms for SAR data correlation but performance was inadequate for an extended mission. To increase performance, JPL undertook a research program to develop the Advanced Digital SAR Processor (ADSP) which implemented a frequency-domain correlation algorithm in custom hardware and was capable of processing 50 megabits per second. The ADSP design was subsequently used in a lower-throughput system recently installed at the University of Alaska, Fairbanks. The SIR-C and RADARSAT missions, however, will employ SAR processors based, to the maximum extent possible, on general-purpose, commercially-available computing components. Beginning with the European Earth Resources Satellite (ERS-1), routine geophysical products will be made from SAR data. A prototype system was installed at the Alaska SAR Facility which will routinely generate ice motion and ice type maps. The SIR-C ground processing system and the Alaska SAR Facility are important precursors for EOS SAR, which will have an order of magnitude greater processing requirements.

Modular multiplication hardware algorithms with a redundant representation and their application to RSA cryptosystem

Radix-2 and radix-4 modular multiplication hardware algorithms are proposed. Numbers are represented in a redundant representation and modular additions are performed without carry propagation. Serial-parallel modular multipliers based on them have a regular cellular array structure with a bit slice feature suitable for VLSI implementation. They are efficient especially in applications, such as an RSA cryptosystem, where modular multiplications are performed iteratively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fast VLSI solution for approximate string matching

A simple hardware algorithm is proposed for the approximate string matching problem, where a string is searched in a large, flat text with a bounded number of insertions, deletions and substitutions. The employed interconnection network is a classical mesh-of-trees, augmented with trees along the main diagonals of the mesh. The area and time bounds are shown, and compared favorably with previous solutions in many cases.

Design of an ultrahigher‐valued biocomputing system based on set‐valued logic networks

AbstractIf multiple‐valued digital systems can be extended to higher‐valued digital systems, potential advantages of high information density and efficient multiple‐valued hardware algorithms will be utilized.This paper presents set‐valued logic networks based on biodevices to construct ultrahigher‐valued digital systems. The biodevices detect specific substrate molecules in solution using specificity enzymes and broadcast specific molecules to perform computation.To design biodevice networks systematically, the concept of set‐valued logic is developed in which molecular information is considered a set of logic values characterized by varieties of molecules. The set‐valued logic enables 2r‐valued computation to be achieved using r kinds of substrate molecules. It is shown that arbitrary set‐valued logic functions can be realized by highly parallel and very regular biodevice networks. Consequently, an approach to a parallel computing system without the restriction of interconnection problems is presented.

A radix-4 modular multiplication hardware algorithm for modular exponentiation

A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient for modular exponentiation with a large modulus, used in public-key cryptosystems such as the RSA cryptosystem. The operands and the result of multiplication which are intermediate results in modular exponentiation are represented in a redundant representation. The computation proceeds in serial-parallel fashion. Each subtraction for the division for residue calculation is embedded in the repeated multiply-add. Each intermediate result is represented in a more redundant representation than that for the operands and the result, so that the number of the required addition/subtractions is reduced. All addition/subtraction are carried out without carry propagation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature and is suitable for VLSI implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient VLSI designs for data transformation of tree-based codes

A class of VLSI architectures for data transformation of tree-based codes is proposed, concentrating on transformation functions used for data compression and decompression. Two algorithms are presented: a sequential algorithm that generates the code bits serially one bit per machine cycle, and a parallel algorithm that generates the entire code bits of a symbol in one machine cycle. The algorithms use the principle of propagation of a token in a reverse binary tree constructed from the original codes. The design approaches are applicable to any binary codes, although the static Huffman code is used as an illustration. A hardware algorithm for generating adaptive Huffman codes is proposed, and a VLSI architecture for implementing the algorithm is described. The high speed of the algorithms ensures that data transformation is done on the fly, as data are being transferred from/to high-speed I/O communication devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 512 16-b bit-serial sorter chip

A hardware algorithm is presented for sorting. This algorithm is based on a highly pipelined bit-serial architecture. The processing time of this sorter is linearly proportional to the number of data. Sorting cells are much smaller and simpler than previously reported sorter cells. A single chip sorting 512 16-b keys was designed with a 2- mu m process and simulated at 240 MHz. For sorting sequences up to 512 keys along, the performance of this sorter is more than 60 times better than previously reported hardware sorters. >

Log-depth circuits for elementary functions using residue number system

A new hardware algorithm for evaluating elementary functions internally using residue arithmetic is proposed. The algorithm is an improved generalization of Beame-Cook-Hoover's log-depth divider for evaluation of all elementary functions. The proposed circuit computes n-bit elementary functions in time proportional to log n. On a residue number system, a polynomial can be evaluated at each residue digit independently. Utilizing this property, each residue digit of an approximation polynomial of the target function is looked up from a small table in parallel. Thus the circuit is faster and smaller than Beame-Cook-Hoover's although both have the same order of computation time O(logn). The circuit based on the algorithm is composed of three parts, i.e., binary-to-residue converter, ROM for table looking-up and residue-to-binary converter. It has a regular structure suitable for VLSI implementation. By changing only the contents of looking-up tables corresponding to the approximation formula, a circuit can compute any elementary function uniformly.

A suggestion for performance improvement in a relational database machine

Database machines are special purpose backend architectures that are designed to support efficiently database management system operations. An important problem in the development of database machines has been that of increasing their performance. Earlier research on the performance evaluation of database machines has indicated that I/O operations constitute a principle performance bottleneck. This is increasingly the case with the advances in multiprocessing and a growth in the volume of data handled by a database machine. One possible strategy to improve the performance of such a system which handles huge volumes of data is to store the data in a compressed form. This can be achieved by introducing VLSI chips for data compression so that data can be compressed and decompressed “on-the-fly”. A set of hardware algorithms for data compression based on the Huffman coding scheme proposed in an earlier work is described. The main focus of this paper is the investigation conducted by the authors to study the effect of incorporating such hardware in a special purpose backend relational database machine. Detailed analytical models of a relational database machine and the analytical results that quantify the performance improvement due to compression hardware are presented.