Abstract
A hardware algorithm is presented for sorting. This algorithm is based on a highly pipelined bit-serial architecture. The processing time of this sorter is linearly proportional to the number of data. Sorting cells are much smaller and simpler than previously reported sorter cells. A single chip sorting 512 16-b keys was designed with a 2- mu m process and simulated at 240 MHz. For sorting sequences up to 512 keys along, the performance of this sorter is more than 60 times better than previously reported hardware sorters. >
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