Hardware Accelerators Research Articles

A Scalable Security Approach in IoT Networks: Smart Contracts and Anomaly-based IDS for Gateways using Hardware Accelerators

A Scalable Security Approach in IoT Networks: Smart Contracts and Anomaly-based IDS for Gateways using Hardware Accelerators

Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool with High-Accuracy and Multi-Level Parallelism.

AutoDock Vina (Vina) stands out among numerous molecular docking tools due to its precision and comparatively high speed, playing a key role in the drug discovery process. Hardware acceleration of Vina on FPGA platforms offers a high energy-efficiency approach to speed up the docking process. However, previous FPGA-based Vina accelerators exhibit several shortcomings: 1) Simple uniform quantization results in inevitable accuracy drop; 2) Due to Vina's complex computing process, the evaluation and optimization phase for hardware design becomes extended; 3) The iterative computations in Vina constrain the potential for further parallelization. 4) The system's scalability is limited by its unwieldy architecture. To address the above challenges, we propose Vina-FPGA-cluster, a multi-FPGA-based molecular docking tool enabling high-accuracy and multi-level parallel Vina acceleration. Standing upon the shoulders of Vina-FPGA, we first adapt hybrid fixed-point quantization to minimize accuracy loss. We then propose a SystemC-based model, accelerating the hardware accelerator architecture design evaluation. Next, we propose a novel bidirectional AG module for data-level parallelism. Finally, we optimize the system architecture for scalable deployment on multiple Xilinx ZCU104 boards, achieving task-level parallelism. Vina-FPGA-cluster is tested on three representative molecular docking datasets. The experiment results indicate that in the context of RMSD (for successful docking outcomes with metrics below 2Å), Vina-FPGA-cluster shows a mere 0.2% lose. Relative to CPU and Vina-FPGA, Vina-FPGA-cluster achieves 27.33× and 7.26× speedup, respectively. Notably, Vina-FPGA-cluster is able to deliver the 1.38× speedup as GPU implementation (Vina-GPU), with just the 28.99% power consumption.

SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA

<abstract><p>Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph-based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware-friendly. Second, a load-balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre-fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283$ \times $, 13$ \times $, and 2.3$ \times $.</p></abstract>

JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration

JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration

Impact of High-Level-Synthesis on Reliability of Artificial Neural Network Hardware Accelerators

Impact of High-Level-Synthesis on Reliability of Artificial Neural Network Hardware Accelerators

A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis

A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis

Hardware accelerators for processing clusters in binary vectors

The paper suggests fast hardware accelerators for discovering clusters of zeros and/or ones in binary vectors. Any cluster is composed of successive bits with the same value (either 1 or 0). Search for such segments is required in many practical problems, for example, coding, data, and image processing. The proposed solutions enable, for a given vector, answering such questions as how many one/zero clusters can be found; what is the largest number of consecutive ones/zeros; what is the number of clusters having k consecutive ones/zeros; is the vector only composed of segments with exactly k consecutive ones/zeros; and some others. The relevant practical applications, for which acceleration is required, are also discussed. The paper suggests two core architectural solutions that are based on combinational and iterative networks of gates. Each network is modeled in software (C++ language) and then specified in a hardware-description language (VHDL), synthesized, and implemented in FPGA. Finally, the results of the circuits’ evaluations and comparisons are presented.

Hardware Acceleration of Crystals-Kyber in Low-Complexity Embedded Systems With RISC-V Instruction Set Extensions

Hardware Acceleration of Crystals-Kyber in Low-Complexity Embedded Systems With RISC-V Instruction Set Extensions

Efficient lightweight cryptography for resource-constrained WSN nodes

In Wireless Sensor Networks (WSN), where resources are scarce, lightweight cryptography is crucial and difficult. The Constrained Application Protocol (CoAP), Field-Programmable Gate Array (FPGA) technology, and a modified RC5 algorithm are used in this study to achieve efficient encryption for WSN nodes. WSN are essential for monitoring temperature, humidity, vibrations, and seismic activity. However, processing capacity, memory, and energy constraints make data security difficult in these networks. CoAP, FPGA, and a modified RC5 algorithm provide security, computational load reduction, and energy efficiency in resource-limited WSN. This research is crucial because it creates cryptographic mechanisms that accommodate WSN unique needs. By protecting data integrity and confidentiality, these mechanisms ensure data transmission security and privacy. Data security and efficiency in WSN require innovative cryptographic, FPGA-based hardware acceleration, and protocol optimization solutions. These methods could improve these vital sensing networks. This research lays the foundation for protecting the accuracy and security of WSN node data collected and transmitted with limited resources while optimizing resource allocation.

A Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays.

Analog resistive random access memory (RRAM) devices enable parallelized nonvolatile in-memory vector-matrix multiplications for neural networks eliminating the bottlenecks posed by von Neumann architecture. While using RRAMs improves the accelerator performance and enables their deployment at the edge, the high tuning time needed to update the RRAM conductance states adds significant burden and latency to real-time system training. In this article, we develop an in-memory discrete Fourier transform (DFT)-based convolution methodology to reduce system latency and input regeneration. By storing the static DFT/inverse DFT (IDFT) coefficients within the analog arrays, we keep digital computational operations using digital circuits to a minimum. By performing the convolution in reciprocal Fourier space, our approach minimizes connection weight updates, which significantly accelerates both neural network training and interference. Moreover, by minimizing RRAM conductance update frequency, we mitigate the endurance limitations of resistive nonvolatile memories. We show that by leveraging the symmetry and linearity of DFT/IDFTs, we can reduce the power by 1.57 × for convolution over conventional execution. The designed hardware-aware deep neural network (DNN) inference accelerator enhances the peak power efficiency by 28.02 × and area efficiency by 8.7 × over state-of-the-art accelerators. This article paves the way for ultrafast, low-power, compact hardware accelerators.

An LSTM-based Neural Network Wearable System for Blood Glucose Prediction in People with Diabetes.

This article proposes the first hardware implemen-tation of a low-power LSTM neural network targeting a wearable medical device designed to predict blood glucose at a 30-minute horizon. This work aims to reduce energy consumption by propos-ing new activation functions that target hardware implementation. On top of this proposal, we also prove there is room for improve-ment in energy consumption by applying neural network optimiza-tions at the algorithmic, such as quantization, and architecture level, LSTM hyperparameters, that consider the target hardware. To validate our proposal, we devise an optimized version of the neural network aimed to be wearable and, therefore, to reduce its energy consumption while preserving its accuracy as much as possible. The hardware is implemented on a Xilinx Virtex-7 FPGA VC707 Evaluation Kit. It is compared with (i) a faithful design of the original neural network implemented on the same evaluation kit, (ii) three state-of-the-art LSTM-based FPGA implementations, and (iii) software implementations running in cutting-edge smartphones:OnePlus NordTM and an Apple iPhone 13 ProTM with artificial in-telligence hardware accelerators. Our proposal consumes between ×1020 and ×7 less energy than the software implementations, being the most efficient system compared to the smartphones. On the other hand, its energy efficiency, measured in GFLOP/J, is between ×2.84 and ×7.82 greater than other state-of-the-art LSTM implementations, proving to be the most suitable implementation for a wearable system for blood glucose prediction.

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption

High Speed Binary Neural Network Hardware Accelerator Relied on Optical NEMS

High Speed Binary Neural Network Hardware Accelerator Relied on Optical NEMS

Data- and Physics-driven Deep Learning Based Reconstruction for Fast MRI: Fundamentals and Methodologies.

Magnetic Resonance Imaging (MRI) is a pivotal clinical diagnostic tool, yet its extended scanning times often compromise patient comfort and image quality, especially in volumetric, temporal and quantitative scans. This review elucidates recent advances in MRI acceleration via data and physics-driven models, leveraging techniques from algorithm unrolling models, enhancement-based methods, and plug-and-play models to the emerging full spectrum of generative model-based methods. We also explore the synergistic integration of data models with physics-based insights, encompassing the advancements in multi-coil hardware accelerations like parallel imaging and simultaneous multi-slice imaging, and the optimization of sampling patterns. We then focus on domain-specific challenges and opportunities, including image redundancy exploitation, image integrity, evaluation metrics, data heterogeneity, and model generalization. This work also discusses potential solutions and future research directions, with an emphasis on the role of data harmonization and federated learning for further improving the general applicability and performance of these methods in MRI reconstruction.

DETECTION OF MALICIOUS ACTIVITY USING A NEURAL NETWORK FOR CONTINUOUS OPERATION

This article describes the problem of detecting malicious programs in running systems of users of mobile applications. Because users can download any application on their phone, which over time can pull up additional settings, which can store malicious routines for monitoring both personal life and their personal data, such as logins, passwords, bank data. The detection of such routines is based on dynamic analysis and is formulated as a weakly controlled problem. The article contains an analysis of information on the development of researchers who worked on detection models and methods such as: statistical and dynamic intrusion detection methods, anomaly detection model, settings classification methods, machine and deep learning methods. Machine learning, and especially deep learning, has become an extremely useful and interesting topic in cybersecurity over the past few years. In this context, the detection of malicious software has received considerable attention. The article considers the problem of detecting the activity of malicious software of mobile operating systems in the time domain by analyzing behavioral sequences of a large amount of industrial data. When malware executes on a system, its behavior consists of a series of distinct actions placed along the time axis, and there is only a subsequence of actions that lead to malicious activity. Very often, malicious software does not manifest itself immediately, and at some point in the execution, malicious activity is formed. Therefore, the main task and difficulty is to identify such a subsequence in the entire sequence of events. Due to this, it is proposed to develop a behavior model that would analyze the dynamic behavior of the program in the system during execution. For this, a sequence of API/function calls generated by the program at runtime is used as input data and a recurrent neural network (RNN) architecture is proposed to detect malicious activity. The article describes the training method of the proposed model and provides verification of its performance on a large sample of industrial data consisting of a large number of samples generated on the emulator farm. Many mobile phone vendors strive for hardware acceleration on the device to provide better support. Therefore, it can be considered that the deployment of a model based on RNM directly on the device as one of the security levels can become a viable solution. The test data of the model described in the article show sufficiently high positive results when detecting malicious activities.

Containerized In-Storage Processing Model and Hardware Acceleration for Fully-Flexible Computational SSDs

Containerized In-Storage Processing Model and Hardware Acceleration for Fully-Flexible Computational SSDs

Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform

Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform

FPGA-based Lightweight QDS-CNN System for sEMG Gesture and Force Level Recognition.

Deep learning (DL) has been used for electromyographic (EMG) signal recognition and achieved high accuracy for multiple classification tasks. However, implementation in resource-constrained prostheses and human-computer interaction devices remains challenging. To overcome these problems, this paper implemented a low-power system for EMG gesture and force level recognition using Zynq architecture. Firstly, a lightweight network model structure was proposed by Ultra-lightweight depth separable convolution (UL-DSC) and channel attention-global average pooling (CA-GAP) to reduce the computational complexity while maintaining accuracy. A wearable EMG acquisition device for real-time data acquisition was subsequently developed with size of 36mm×28mm×4mm. Finally, a highly parallelized dedicated hardware accelerator architecture was designed for inference computation. 18 gestures were tested, including force levels from 22 healthy subjects. The results indicate that the average accuracy rate was 94.92% for a model with 5.0k parameters and a size of 0.026MB. Specifically, the average recognition accuracy for static and force-level gestures was 98.47% and 89.92%, respectively. The proposed hardware accelerator architecture was deployed with 8-bit precision, a single-frame signal inference time of 41.9μs, a power consumption of 0.317W, and a data throughput of 78.6 GOP/s.

Real-Time Stereo Vision Hardware Accelerator: Fusion of SAD and Adaptive Census Algorithm

Real-Time Stereo Vision Hardware Accelerator: Fusion of SAD and Adaptive Census Algorithm

A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators

A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators