Hard Real-time Requirements Research Articles

PyIgH : A unified architecture of IgH EtherCAT Master based on Python considering hard real-time constraints

The increasing demand for rapid application development tools, especially those employing high-level languages such as Python, has underscored the importance of utilizing a wide array of popular libraries while addressing real-time constraints in distributed hardware systems. This paper introduces PyIgH, a unified architecture of an IgH EtherCAT master based on Python, specifically designed to satisfy hard real-time requirements in an EtherCAT network. Implemented as a Python module, PyIgH exposes the functionalities and capabilities of an open-source EtherCAT master, facilitating seamless configuration and control of EtherCAT slave devices within the Python runtime environment. Real-time adaptation of the POSIX library, encapsulated within Python, is also utilized to satisfy the timing requirements of EtherCAT. The feasibility of the proposed approach is verified by analyzing the real-time performance in terms of periodicity and in-controller delay of the EtherCAT control task with a 1 kHz cycle. Experimental results demonstrate that PyIgH is suitable for hard real-time applications and serves as a valid alternative to conventional low-level EtherCAT masters. Additionally, a practical application involving motion control of a six-axis collaborative robot showcases consistent performance of PyIgH within a real-time multi-tasking environment.

Speeding Task Allocation Search for Reconfigurations in Adaptive Distributed Embedded Systems Using Deep Reinforcement Learning.

A Critical Adaptive Distributed Embedded System (CADES) is a group of interconnected nodes that must carry out a set of tasks to achieve a common goal, while fulfilling several requirements associated with their critical (e.g., hard real-time requirements) and adaptive nature. In these systems, a key challenge is to solve, in a timely manner, the combinatorial optimization problem involved in finding the best way to allocate the tasks to the available nodes (i.e., the task allocation) taking into account aspects such as the computational costs of the tasks and the computational capacity of the nodes. This problem is not trivial and there is no known polynomial time algorithm to find the optimal solution. Several studies have proposed Deep Reinforcement Learning (DRL) approaches to solve combinatorial optimization problems and, in this work, we explore the application of such approaches to the task allocation problem in CADESs. We first discuss the potential advantages of using a DRL-based approach over several heuristic-based approaches to allocate tasks in CADESs and we then demonstrate how a DRL-based approach can achieve similar results for the best performing heuristic in terms of optimality of the allocation, while requiring less time to generate such allocation.

An Enhanced Industrial Wireless Communication Network for Hard Real Time Performance Substation Automation Purposes

Wireless communication network (WCN) technologies are charming solutions to bolster the conventional electrical substations with the intention of take the fashion of smart substation such as reduction in equipment, minimize the maintenance costs, flexibility, and expansion. However, the harsher challenge facing WCN employing in the electrical substation is the real time protection of substation automation system (SAS) for the high voltage devices in terms of the latency and the reliability in particular the substations of old topologies. This work suggests WCN including special types of the intermediate devices (Switched-Access Points (S-AP) and Multi Wireless Domain- Access Point (MWD-AP)) to address the expected packets congestion by creating independent wireless channels domains offering wireless channels reliability in such network topology that deals with real time data traffic (RT) and the non-real time data traffic (NRT). Riverbed modeler is adopted to simulate the model of the electrical substation network due to the rich tools of communication networks in term of industry environment. The results indicate, the suggested WCN can handle the hard real time requirements of protection from latency and data reliability points of view in case of basic capacity of 802.11a/n standards at the level of ≤ 4 msec and high data reliability.

High Accuracy Software-Based Clock Synchronization Over CAN

In distributed real-time communication systems, common knowledge of the global time is crucial. It prevents message violations on the bus and allows independent components to collaborate within a real-time system on a timely basis. Systems with hard real-time requirements need to have high precision and accuracy of time. This is achieved by hardware-supported frame time-stamping mechanisms as found in dedicated protocols, such as time-triggered CAN (TTCAN), Flexray, and time-sensitive networking (TSN)-enabled Ethernet. However, many microcontroller units are not specifically designed to provide such a hardware-based solution at the communication interface. Therefore, a software-based implementation of the time synchronization algorithm is needed. Nevertheless, some commercial off-the-shelf (COTS) microcontroller units already provide an IEEE 1588-enabled Ethernet interface, including a high-precision timer module with rate correction. This module can be used for time synchronization purposes to align a set of distributed clocks via various communication interfaces. This article investigates the accuracy of software-based and hardware-supported time synchronization algorithm over the controller area network (CAN) protocol using a COTS microcontroller. As a result, we present identified jitter and delay sources as well as the achieved time accuracy. We show that using an advanced timer module combined with additional system knowledge allows submicrosecond precision and accuracies.

Predicting regenerative chatter in milling with hardware-in-the-loop simulation using a dexel-based cutting model

This article proposes a new model for simulating the interaction between cutting process and machine tool in real-time. The purpose of the model is to be coupled with a real CNC (by using hardware-in-the-loop simulation) in order to consider process forces and to predict regenerative chatter vibrations during virtual commissioning. Therefore a dexel-based workpiece model with adaptive resolution is used for the computation of the chip thickness respectively the cutting forces based on the actual machine tool position and the machining progress on the workpiece. Several simulation experiments are performed to validate the model and to analyze its numerical limits, such as computational accuracy and efficiency. The capability of the model to predict chatter is proven by comparing the simulated critical depth of cut with an analytical solution of the stability lobes. Therefore the dynamics of the machine tool were approximated as a single degree of freedom (SDOF) oscillator. A concluding analysis of the real-time factor confirms the model’s ability to be integrated under hard real-time requirements and with cycle times of just a few milliseconds which are typical of CNCs.

Model-Based Design of Service-Oriented Architectures for Reliable Dynamic Reconfiguration

<div class="section abstract"><div class="htmlview paragraph">Service-oriented architectures (SOAs) are well-established solutions in the IT industry. Their use in the automotive domain is still on the way. Up to now, the automotive domain has taken advantage of service-oriented architectures only in the area of infotainment and not for systems with hard real-time requirements. However, applying SOA to such systems has just started but is missing suitable design and verification methodologies. In this context, we target to include the notion of model-based design to address fail-operational systems. As a result, a model-based approach for the development of fail-operational systems based on dynamic reconfiguration using a service-oriented architecture is illustrated. For the evaluation, we consider an example function of an automatically controlled braking system and analyze the reconfiguration time when the function fails. The reconfiguration time, together with the worst-case execution time (WCET), was determined by a model-based calculation and by simulation. In summary, the proposed approach applied to dynamically reconfigurable systems can meet the design requirements of the ISO 26262.</div></div>

Execution Time of Optimal Controls in Hard Real Time, a Minimal Execution Time Solution for Nonlinear SDRE

Many engineering fields, such as automotive, aerospace, and the emerging challenges towards industry 4.0, have to deal with Real-Time (RT) or Hard Real Time (HRT) systems, where temporal constraints must be fulfilled, to avoid critical behaviours or unacceptable system failures. For this reason, estimation of code's Worst-Case Execution Time (WCET) has received lots attention because in RT systems a fundamental requirement is to guarantee at least a temporal upper bound of the code execution for avoiding any drawbacks. However, until now there is no approved method to compute extremely tight WCET. Nowadays, indeed, HRT requirements are solved via hardware, using multi-cores embedded boards that allow the computation of the deterministic Execution Time (ET). The availability of these embedded architectures has encouraged the designers to look towards more computationally demanding optimal control techniques for RT scenarios, and to compare and analyze performances also evaluating a tight WCET. However, this area still lacks deep investigations. This paper has the intent of analysing results regarding the choice between three of the most established optimal controls (LQR, MPC, SDRE), providing the first link between WCET analysis and control algorithms performances. Moreover, this work shows how it is also possible to obtain a minimal ET solution for the nonlinear SDRE controller. The results might be useful for future implementations and for coping with Industry 4.0 emerging challenges. Furthermore, this approach can be useful in control system engineering field, especially in the design stage for RT or HRT systems, where temporal bounds have to be fulfilled jointly with all the other application's specifications.

A Fault-Tolerant Ethernet for Hard Real-Time Adaptive Systems

Distributed embedded systems (DESs) that perform critical tasks in unpredictable environments must be reliable, hard real-time, and adaptive. Since a DES comprises nodes that rely on a network, the network must provide adequate support: it must be reliable, convey messages on time, and meet new real-time requirements as the nodes adapt. Ethernet is ill-suited for such hard real-time adaptive systems, but it can be made suitable. The flexible time-triggered (FTT) paradigm already supports hard real-time message exchanges and the necessary flexibility to meet evolving hard real-time requirements, but its Ethernet implementations had reliability limitations. To address these, we designed FTT replicated star for Ethernet (FTTRS), a communication subsystem that tolerates permanent and transient faults, even if they occur simultaneously, while keeping the paradigm's key features: support for both the timely exchange of periodic and sporadic real-time messages, and support for updating the real-time parameters of these messages at runtime. In this paper, we present FTTRS, the first Ethernet-based communication subsystem specifically designed for highly reliable hard real-time adaptive DESs.

Desarrollo de Sistemas Distribuidos de Tiempo Real y de Criticidad Mixta a través del Estándar DDS

<p>El uso de middleware de distribución facilita la programación de sistemas distribuidos de tiempo real heterogéneos, y por extensión también puede facilitar la generación automática de código como parte de una estrategia de desarrollo basada en modelos. Sin embargo, esta clase de middleware presenta una complejidad añadida que dificulta su uso en sistemas con ciertos requisitos de criticidad o de tiempo real. En este trabajo se hace una revisión de algunos estudios previos en los que se muestra la posibilidad de utilizar un middleware de distribución centrado en los datos (DDS, Data Distribution Service) para la integración de aplicaciones con criticidad mixta en sistemas distribuidos.</p>

A Motion Cueing Algorithm With Look-Ahead and Driver Characterization: Application to Vertical Car Dynamics

Driving simulators are nowadays a widely used tool in the automotive industry. In particular, the need for safe and repeatable conditions in automated driving testing is now defining a new challenge: to extend the use of the tool to nonprofessional drivers. Quality of the motion control strategies in generating both realistic and feasible inputs to the driver is therefore, more than ever, a crucial aspect. The motion strategies are implemented in the so-called motion cueing algorithms (MCAs). A recently proposed effective approach to MCA is based on model predictive control (MPC), as it is well suited to solve constrained optimal control problems and to take advantage of models of the human sensing system. However, the predictive aspect of the algorithm has not been exploited yet, due to the hard real-time requirement when using long prediction windows. In this paper, a real-time implementation of an MPC-based MCA with predictive feature is presented, endowed with an on-line switching policy to a nonpredictive algorithm when the expected driver behavior is considered unreliable. The motion action based on the actual driver behavior and the expected one are considered in the same procedure, thus fully exploiting the availability of a perceptive model. An optimal tuning procedure is also proposed, based on a multiobjective optimization, where both performance improvement due to the prediction exploitation, and robustness to varying driver behaviour are considered. Finally, a characterization of the driver skill level is proposed and validated in an experimental environment for the specific case of the vertical DOF.

Towards optimal solutions for the low power hard real-time task allocation on multiple heterogeneous processors

The usage of heterogeneous multicore platforms is appealing for applications, e.g. hard real-time systems, due to the potential reduced energy consumption offered by such platforms. However, even in such platforms the power wall phenomena still imposes limits to performance. Hard real-time systems are part of life critical environments and reducing the energy consumption on such systems is an onerous and complex process. We tackle the problem from the perspective of different representative integer programming mathematical formulations and their interplay on the search for optimal solutions for Rate Monotonic (RM) and Earliest Deadline First (EDF) scheduling algorithms. The proposed models are based on a well-established formulation in the operational research literature, namely, the Multilevel Generalized Assignment Problem (MGAP). This paper, therefore, assesses the problem of finding optimal allocations and frequency assignments of hard real-time tasks among heterogeneous processors targeting low power consumption, but taking into account timing constraints. Computational experiments show that finding optimal solutions reduces the estimated energy consumption of the evaluated cases when compared to state-of-the-art algorithms. • Representative theoretical models of several hard real-time scheduling policies. • New application of well-known classical combinatorial optimization problem: MGAP. • Applicability on embedded systems with low power and hard real-time requirements. • Optimal workload partitioning on heterogeneous processors in project time. • Computational experiments on finding optimal solutions for the proposed models.

Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements

The complexity of embedded application design is increasing with growing user demands. In particular, automotive embedded systems are highly complex in nature, and their functionality is realized by a set of periodic tasks. These tasks may have hard real-time requirements and communicate over an interconnect. The problem is to efficiently co-schedule task execution on cores and message transmission on the interconnect so that timing constraints are satisfied. Contemporary works typically deal with zero-jitter scheduling, which results in lower resource utilization, but has lower memory requirements. This article focuses on jitter-constrained scheduling that puts constraints on the tasks jitter, increasing schedulability over zero- jitter scheduling. The contributions of this article are: 1) Integer Linear Programming and Satisfiability Modulo Theory model exploiting problem-specific information to reduce the formulations complexity to schedule small applications. 2) A heuristic approach, employing three levels of scheduling scaling to real-world use-cases with 10000 tasks and messages. 3) An experimental evaluation of the proposed approaches on a case-study and on synthetic data sets showing the efficiency of both zero-jitter and jitter- constrained scheduling. It shows that up to 28% higher resource utilization can be achieved by having up to 10 times longer computation time with relaxed jitter requirements.

Hardware-accelerated analysis of real-time Networks-on-Chip

A real-time Network-on-Chip (NoC) must guarantee that it is able to execute a set of tasks and deliver the communication packets that they generate, all within the respective deadlines even under a worst-case scenario. End-to-End Response Time Analysis (E2ERTA) is a mathematical formulation that can be used to test whether a particular NoC configuration is able to guarantee the timely execution of tasks and delivery packets. The complexity of E2ERTA calculation increases with the increase of the number of tasks and packet flows, and with the core count of the NoC. This paper presents an approach to accelerate E2ERTA calculations through the use of custom hardware and efficient implementation of its mathematical operations. We explore the performance of the proposed approach, and analyse its effectiveness against the state-of-the-art in the field. The results show a significant improvement in testing NoC guarantees, thus potentially enabling the use of E2ERTA as a fast and guaranteed deterministic admission controller for open and dynamic real-time systems. As a case-study, we integrate the proposed approach to a NoC optimisation framework aiming to accelerate the search for NoC configurations that meet all the NoC’s hard real-time requirements.

A real-time, MPC-based Motion Cueing Algorithm with Look-Ahead and driver characterization

The use of dynamic driving simulators is nowadays common practice in the automotive industry. The effectiveness of such devices is strongly related to their capabilities of well reproducing the driving sensations, hence it is crucial that the motion control strategies generate both realistic and feasible inputs to the platform. Such strategies are called Motion Cueing Algorithms (MCAs). Model Predictive Control (MPC) has been successfully applied to MCAs, being well suited to solve constrained optimal control problems. However, the predictive aspect of the algorithm has not been exploited effectively yet, mainly due to the hard real-time requirement when using a significantly long prediction window. In this paper, a real time implementation of the so called Look-Ahead (LA) strategy is presented, that is based on an effective manipulation of the reference along the prediction horizon, and on an on-line switching policy to a Non-Look-Ahead strategy when the expected driver behavior is not reliable. An optimal tuning of the MCA is computed by means of a multi-objective optimization, where both performance improvement due to the prediction exploitation, and robustness to varying driver behavior are taken into account. Finally, a characterization of the driver skill level is proposed and validated in experimental environment.

No latency feedback controller coupled to real-time physical models using programmable hardware

Over the last years, advances in technology and methodology made it possible to simulate and synthesize highly realistic finite difference (FD) models in real-time or close to real-time. Still, most conventional processing platforms introduce latency to the signal processing chain due to sequential processing and/or communication protocol timing and throughput restrictions. This can act as a severe penalty when developing expressive controller interfaces for large geometry physical models. Using field programmable gate array (FPGA) hardware enables highly customized interface and FD model designs that are able to meet hard real-time requirements even for large physical models. In this work, a modified five-string banjo coupled to a real-time physical modeling synthesis application running on an FPGA development board is presented. The proposed methodology is an extension of an existing PCIe enabled interface which was primarily developed for research applications. The new interface is aimed at facilitating expressive interaction for musical purposes. The bi-directional excitation and feedback is realized using standard electro-mechanical sensors and actuators, making it possible to connect the string vibration of the modified banjo to arbitrary geometries as well as capturing the response of the modeled structure and feeding it back to the acoustic instrument. FD-models of different shapes and materials are implemented resulting in physically impossible instrument configurations yielding unique tone production capabilities.

PKI Deployment Challenges and Recommendations for ICS Networks

Different types of Control Systems used for Industrial production are broadly called Industrial Control Systems (ICS) (n.d.). These include Supervisory Control and Data Acquisition (SCADA) Systems and Distributed Control Systems (DCS). ICS typically perform the “Command and Control” operations required for smooth functioning of machines in industrial production. They are widely used in Critical infrastructures such as power generation and distribution systems, Oil and Gas plants, Chemical factories and various other manufacturing facilities. Traditionally, ICS used proprietary protocols and operated in isolation. Perimeter security was considered enough as the only means to compromise these systems was via physical access to the systems. However, increased standardization, open architecture adoption and connectivity to enterprise networks as well as internet opened up these systems for a wide range of audience and enabled remote attacks. In this new operation landscape, it is imperative that newer means of securing the networks are adopted continuously. One of the security considerations for the ICS networks is the communication paths used by these networks. Public Key Infrastructure (PKI) (n.d.) plays a key role in securing the communication of ICS networks. Using Digital Certificates, PKI provides a mechanism to verify the identity of all the entities on a network and also ensures that the information is shared securely between communicating entities. PKI is a proven mechanism for secure communication and is widely used in many organizations. However, PKI as a solution to ICS security is challenging due to factors such as resource constrained environments, bandwidth considerations and hard real-time communication requirements. This paper intends to focus on key challenges in Digital Certificate management and correct deployment of PKI in ICS networks and will also present recommendations to overcome these challenges without compromising the basic functionalities of ICS.

Adaptive Workload Management in Mixed-Criticality Systems

Due to the efficient resource usage of integrating tasks with different criticality onto a shared platform, the integration with mixed-criticality tasks is becoming an increasingly important trend in the design of real-time systems. One challenge in such a mixed-criticality system is to maximize the service for low-critical tasks, while meeting the timing constraints of high-critical tasks. In this article, we investigate how to adaptively manage the low-critical workload during runtime to meet both goals, that is, providing the service for low-critical tasks as much as possible and guaranteeing the hard real-time requirements for high-critical tasks. Unlike previous methods, which enforce an offline bound towards the low-critical workload, runtime adaptation approaches are proposed in which the incoming workload of low-critical tasks is adaptively regulated by considering the actual demand of high-critical tasks. This actual demand of the high-critical tasks, in turn, is adaptively updated using their historical arrival information. Based on this adaptation scheme, two scheduling policies—the priority-adjustment policy and the workload-shaping policy—are proposed to do the workload management. In order to reduce online management overhead, a lightweight scheme with O ( n · log ( n )) complexity is developed. Extensive simulation results are presented to demonstrate the effectiveness of our proposed workload management approaches.

Robust H∞ filtering for a spacecraft attitude determination system with affine LPV approach

A novel approach is presented in this paper for the filtering design in a spacecraft attitude determination system (ADS), which is equipped with a star sensor and three-axis gyros. Firstly, the ADS workflow and its mathematical model components are described. Then, the ADS state-space model is established as a linear parameter varying (LPV) system, and its matrices are assumed to affinely depend on time-varying parameters, i.e. three-axis angular rates. Secondly, system uncertainties and non-Gaussian noises in the spacecraft ADS are considered, and a parameter-dependent robust H∞ filter is designed based on the established LPV model. This filtering design is then transformed as an optimisation process in terms of linear matrix inequalities (LMIs) which is numerically tractable. At last, results from both simulations and hardware-in-the-loop tests with simulated star-tracker measurements are presented. It can be observed that, compared with the Kalman filter, the proposed filtering method achieves more robust results with considering model uncertainties and non-Gaussian noises, which is closer to practical situations. Also, it is more computationally efficient than the Kalman filter, which is very demanding with hard real-time requirement.

Memory Access Scheduling for a Smart TV

A smart TV system-on-chip (SoC) has very heavy computation and memory demands that must be met with low-cost components. As a result, there is potentially an extremely high utilization of the channel between the SoC and its memory chip. This paper presents the design of a new memory access scheduler customized for the type of memory traffic typically encountered with smart TVs. This includes special accumulated hard real-time graphics requirements, user response-sensitive soft real-time requirements, and the need to provide high memory throughput and priority-handling capabilities even under extremely heavy memory traffic conditions. The simulation results show that the proposed memory access scheduler is able to achieve up to 98% of the ideal upper bound memory throughput when faced with extremely heavy memory traffic—this is a significant improvement over previous schedulers. Novel future prediction and light-handed priority handling methods are used to achieve these results while satisfying the unique real-time requirements of smart TVs.

GPU-assisted HEVC intra decoder

The added encoding efficiency and visual quality offered by the High Efficiency Video Coding (HEVC) standard is attained at the cost of a significant computational complexity of both the encoder and the decoder. In particular, the considerable amount of intra prediction modes that are now considered by this standard, together with the increased complexity of the adopted block coding tree structures using a larger diversity of transforms imposes demanding computational efforts that can hardly be satisfied by current general-purpose processors to attain hard real-time requirements. Furthermore, the strict data dependencies that are imposed make parallelization a difficult and hardly efficient option with conventional approaches. To circumvent this adversity, this paper exploits Graphics Processing Units (GPUs) to accelerate the intra decoding procedure in HEVC, encompassing the most demanding modules of the decoder (i.e., de-quantization, inverse transform, intra prediction, deblocking filter, and sample adaptive offset). The presented approaches comprehensively exploit both coarse and fine-grained parallelization opportunities in an integrated perspective by re-designing the execution pattern of the involved modules, while simultaneously coping with their inherent computational complexity and strict data dependencies. As a result, the proposed parallelization, which is fully compliant with the HEVC standard, has shown to be a remarkable viable approach, being capable of satisfying hard real-time requirements by processing each Ultra HD 4 K intra frame in less than 25 ms (about 40 fps).