Hard Real-time Constraints Research Articles

Optimal Dynamic Voltage Scaling in Energy-Limited Nonpreemptive Systems with Real-Time Constraints

Dynamic voltage scaling is used in energy-limited systems as a means of conserving energy and prolonging their life. We consider a setting in which the tasks performed by such a system are nonpreemptive and aperiodic. Our objective is to control the processing rate over different tasks so as to minimize energy subject to hard real-time processing constraints. Under any given task scheduling policy, we prove that the optimal solution to the offline version of the problem can be efficiently obtained by exploiting the structure of optimal sample paths, leading to a new dynamic voltage scaling algorithm termed the critical task decomposition algorithm (CTDA). The efficiency of the algorithm rests on the existence of a set of critical tasks that decompose the optimal sample path into decoupled segments within which optimal processing times are easily determined. The algorithm is readily extended to an online version of the problem as well. Its worst-case complexity of both offline and online problems is O(N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> )

QoS-supported On-chip Communication for Multi-processors

We present a Quality of Service (QoS)-supported on-chip communication that increases the shared communication resources for multi-processor systems on chip. Time-critical embedded systems require tight guaranteed services in terms of throughput, latency etc. in order to comply to hard real-time constraints. Typically, guaranteed-service schemes require dedicated/reserved resources (i.e. links) for communication and thus suffer from low resource utilization. So improving the bandwidth utilization by using the unused bandwidth among the other competing transactions in a fair fashion is an important issue. To the best of our knowledge, we are presenting the first approach for on-chip communication that provides a high resource utilization under a transaction-specific, flexible communication scheme. It provides tight time-related guarantees through our bounded arbitration scheme considering the lower and the upper bounds for each type of transactions. We demonstrate its advantages by means of a complete MPEG4 video decoder case study analysis and achieve under certain constraints a bandwidth utilization of up to 100% and 97% on average with a guaranteed 100% bandwidth. Thus, we provide an on-chip communication scheme that provides high bandwidth uti lization while providing tight guarantee.

REAL-TIME STEREOVISION BY AN INTEGRATED SENSOR

This paper concerns the integration of a complex vision algorithm on a dedicated architecture. Perception is required on a vehicle (robot or car), especially in order to detect obstacles along a trajectory for a robot or on the road for a car. This function must satisfy very hard real-time constraints so that an avoidance strategy could be executed by the onboard system on a robot or by a driver on a car: it is required to detect obstacles at 100Hz. Several sensors have been used to acquire perceptual data from which obstacles are detected: we propose to use a stereovision sensor. This algorithm is so complex that it must be integrated on a dedicated architecture to provide a high resolution 3D reconstruction of the environment at 100Hz. At first, this paper describes a correlation-based stereovision algorithm, and a generic architecture including several FPGA-based boards, designed to execute visual functions at very high frequency. Then we propose a strategy to implement our stereovision algorithm on this computing unit, with four FPGA-based boards.

Non-rigid alignment of pre-operative MRI, fMRI, and DT-MRI with intra-operative MRI for enhanced visualization and navigation in image-guided neurosurgery

Objective: The usefulness of neurosurgical navigation with current visualizations is seriously compromised by brain shift, which inevitably occurs during the course of the operation, significantly degrading the precise alignment between the pre-operative MR data and the intra-operative shape of the brain. Our objectives were (i) to evaluate the feasibility of non-rigid registration that compensates for the brain deformations within the time constraints imposed by neurosurgery, and (ii) to create augmented reality visualizations of critical structural and functional brain regions during neurosurgery using pre-operatively acquired fMRI and DT-MRI.Materials and methods:Eleven consecutive patients with supratentorial gliomas were included in our study. All underwent surgery at our intra-operative MR imaging-guided therapy facility and have tumors in eloquent brain areas (e.g. precentral gyrus and cortico-spinal tract). Functional MRI and DT-MRI, together with MPRAGE and T2w structural MRI were acquired at 3 T prior to surgery. SPGR and T2w images were acquired with a 0.5 T magnet during each procedure. Quantitative assessment of the alignment accuracy was carried out and compared with current state-of-the-art systems based only on rigid registration.Results:Alignment between pre-operative and intra-operative datasets was successfully carried out during surgery for all patients. Overall, the mean residual displacement remaining after non-rigid registration was 1.82 mm. There is a statistically significant improvement in alignment accuracy utilizing our non-rigid registration in comparison to the currently used technology (p<0.001).Conclusions:We were able to achieve intra-operative rigid and non-rigid registration of (1) pre-operative structural MRI with intra-operative T1w MRI; (2) pre-operative fMRI with intra-operative T1w MRI, and (3) pre-operative DT-MRI with intra-operative T1w MRI. The registration algorithms as implemented were sufficiently robust and rapid to meet the hard real-time constraints of intra-operative surgical decision making. The validation experiments demonstrate that we can accurately compensate for the deformation of the brain and thus can construct an augmented reality visualization to aid the surgeon.

Optimisation de performance pour des systèmes temps réel stricts à priorité fixe

Many real-time systems must simultaneously handle hard real-time constraints and Quality of Service constraints. Thus, a performance criterion must be optimized for some tasks while meeting all deadlines for hard real-time tasks. For that purpose, we present a generic Branch & Bound method dedicated to hard real-time fixed-priority schedulers. Our approach is based on a generic algorithm that defines common functions to any performance criteria. Only few functions need to be specialized to deal with a specific criterion. We then present such a specialization for minimizing the weighted average response time of tasks.

Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip

We present a functional partitioning method for low power real-time embedded systems. The goal is to partition the system-level specification of a set of task graphs to realise a distributed system whose constituent nodes are systems-on-a-chip (SOCs). The proposed technique merges partitioning and system synthesis into one integrated process, implemented within a genetic algorithm. This technique satisfies both the hard real-time constraints and each SOC area constraint, and performs multi-objective optimisation, with multiple distributed system architectures produced that trade off overall system price and power consumption. Experimental results show the efficacy of the technique.

Design for Timing Predictability

A large part of safety-critical embedded systems has to satisfy hard real-time constraints. These need sound methods and tools to derive run-time guarantees that are not only reliable but also prec...

Classification of Power Quality Events Using Optimal Time-Frequency Representations—Part 2: Application

Classification of power-quality (PQ)-related voltage and current waveform disturbances is a key task for power system monitoring. A new method based on the optimized time-frequency representation (TFR) has been proposed in the first paper of this two-paper series. This paper (the second paper) presents a case study of PQ event classification with the proposed method. The classification algorithm has been successfully tested with 860 real world PQ events that cover five classes, achieving a recognition rate of 98%. The algorithm is implemented on a digital signal processor (DSP) based hardware system and optimized according to the DSP architecture to meet the hard real-time constraints. The DSP-based system is capable of processing a five-cycle (83.3 ms) PQ waveform within 11.2 ms. The real-time computing capability of the algorithm has been verified with this result. The scalability of this method is also discussed.

Scheduling algorithms based on weakly hard real-time constraints

The problem of scheduling weakly hard real-time tasks is addressed in this paper. The paper first analyzes the characters of µ-pattern and weakly hard real-time constraints, then, presents two scheduling algorithms, Meet Any Algorithm and Meet Row Algorithm, for weakly hard real-time systems. Different from traditional algorithms used to guarantee deadlines, Meet Any Algorithm and Meet Row Algorithm can guarantee both deadlines and constraints. Meet Any Algorithm and Meet Row Algorithm try to find out the probabilities of tasks breaking constraints and increase task's priority in advance, but not till the last moment. Simulation results show that these two algorithms are better than other scheduling algorithms dealing with constraints and can largely decrease worst-case computation time of real-time tasks.

Ownership types for safe region-based memory management in real-time Java

The Real Time Specification for Java (RTSJ) allows a program to create real-time threads with hard real-time constraints. Real-time threads use region-based memory management to avoid unbounded pauses caused by interference from the garbage collector. The RTSJ uses runtime checks to ensure that deleting a region does not create dangling references and that real-time threads do not access references to objects allocated in the garbage-collected heap. This paper presents a static type system that guarantees that these runtime checks will never fail for well-typed programs. Our type system therefore 1) provides an important safety guarantee for real-time programs and 2) makes it possible to eliminate the runtime checks and their associated overhead.Our system also makes several contributions over previous work on region types. For object-oriented programs, it combines the benefits of region types and ownership types in a unified type system framework. For multithreaded programs, it allows long-lived threads to share objects without using the heap and without memory leaks. For real-time programs, it ensures that real-time threads do not interfere with the garbage collector. Our experience indicates that our type system is sufficiently expressive and requires little programming overhead, and that eliminating the RTSJ runtime checks using a static type system can significantly decrease the execution time of real-time programs.

An Object-oriented Methodology for Embedded Real-time Systems

The usage of object-oriented methodologies in conjunction with formal description techniques has arisen as a promising way of dealing with the increasing complexity of embedded real-time systems. These methodologies are currently well supported by a set of tools that allow the specification, simulation and validation of the functional aspects of these systems. However, most of these methodologies do not take into account non-functional aspects such as hardware interaction and real-time constraints, which are especially important in the context of this kind of system. Based on our experiences in developing embedded real-time systems, we present a new methodology to design them. This methodology is based on a combination of ideas from different existing methodologies (UML, OCTOPUS, etc.) together with the integration of rate-monotonic analysis in the context of the SDL formal description technique development cycle. Additionally, in order to get this integration, a real-time execution model for SDL is presented to allow us to express hard real-time constraints. The methodology pays special attention to the transition from the object model to the task model, taking into account real-time and hardware integration issues. We also illustrate our proposal by applying it to the development of a multi-handset cordless telephone.

Giotto: a time-triggered language for embedded programming

Giotto provides an abstract programmer's model for the implementation of embedded control systems with hard real-time constraints. A typical control application consists of periodic software tasks together with a mode-switching logic for enabling and disabling tasks. Giotto specifies time-triggered sensor readings, task invocations, actuator updates, and mode switches independent of any implementation platform. Giotto can be annotated with platform constraints such as task-to-host mappings, and task and communication schedules. The annotations are directives for the Giotto compiler, but they do not alter the functionality and timing of a Giotto program. By separating the platform-independent from the platform-dependent concerns, Giotto enables a great deal of flexibility in choosing control platforms as well as a great deal of automation in the validation and synthesis of control software. The time-triggered nature of Giotto achieves timing predictability, which makes Giotto particularly suitable for safety-critical applications.

Integrating Schedulability Analysis and Design Techniques in SDL

The usage of formal description techniques (FDTs) has arisen as a promising way of dealing with the increasing complexity of embedded real-time systems. However, FDTs do not take into account non-functional aspects, such as the time requirements, that are especially important in the context of this kind of system. In this paper, we present how to integrate real-time analysis in the context of the specification and description language (SDL) FDT. In order to get this integration a real-time execution model for SDL is presented to allow us to express hard real-time constraints and solve SDL real-time anomalies as priority inversion and the access to shared resources. Based on this model, a schedulability analysis for systems specifed in SDL is proposed. Additionally, a set of SDL design techniques are proposed to redesign the system to meet the imposed deadlines in case the system does not meet them. To illustrate our proposals, an example of a computerized numerical control (CNC) machine is presented.

Guaranteeing hard real-time traffic constraints with ATM networks

The advent of high speed networks has introduced opportunities for new distributed applications, such as video conferencing, medical imaging, and telephony over Internet. These applications have stringent performance requirements. Thus, the ability o

Embedded Control Systems Development with Giotto

Giotto is a principled, tool-supported design methodology for implementing embedded control systems on platforms of possibly distributed sensors, actuators, CPUs, and networks. Giotto is based on the principle that time-triggered task invocations plus time-triggered mode switches can form the abstract essence of programming real-time control systems. Giotto consists of a programming language with a formal semantics, and a retargetable compiler and runtime library. Giotto supports the automation of control system design by strictly separating platform-independent functionality and timing concerns from platform-dependent scheduling and communication issues. The time-triggered predictability of Giotto makes it particularly suitable for safety-critical applications with hard real-time constraints. We illustrate the platform-independence and time-triggered execution of Giotto by coordinating a heterogeneous flock of Intel x86 robots and Lego Mindstorms robots.

Automatic effective verification method for distributed and concurrent systems using timed language inclusion

In distributed and concurrent systems, the notions of fairness and time are important as follows: (1)Fairness is a mathematical abstraction in distributed and concurrent systems. Fairness abstracts the details of fair schedulers and the speeds of independent processors. (2)The distributed and concurrent systems have to meet certain hard real-time constraints, and the correctness of them depends on the actual values of the delays.In this paper, we propose the specification and verification method of fairness and time in distributed and concurrent systems as follows: (1)In order to specify fairness, an enable condition and a performed condition are attached to a finite set of states in our proposed specification method. (2)In order to effectively verify distributed and concurrent systems, we restrict timing constraints of timed automaton such that in cycles we must specify timing constraints about the clock variables after they are reset to zero.

Video signal processor scheduling

We consider the problem of scheduling video algorithms onto systems of high-performance video signal processors with hard real-time constraints. We present a compact mathematical formulation which identifies the decision variables and the constraints that are involved. We demonstrate that the scheduling problem is NP-hard in the strong sense. The insight resulting from the mathematical formulation leads to a solution approach in which the problem is decomposed into a time assignment problem and a resource assignment problem. These subproblems are handled with well-known combinatorial optimization techniques from the literature such as shortest paths and graph colouring. The results indicate that the proposed solution approach effectively and efficiently schedules hundreds of operations onto tens of processing elements. Copyright © 2001 John Wiley & Sons, Ltd.

Scheduling multiple variant programs under hard real-time constraints

The paper proposes approximate and evolution based algorithms for scheduling independent, non-preemptable, multiple variant (m-v) tasks on identical processors. Processing and arriving times may differ per task. Optimization criterion is a total number of the executed program variants under hard, real-time constraints. The paper presents also a competitiveness analysis for the corresponding online problem with two processors. In an online case multiple variants tasks arrive one by one and decisions as to the number of variants processed and allocation of variants to either of the identical processors must be taken incrementally. The objective in the online problem is to minimize value of the penalty function defined as the schedule length for accepted variants plus the sum of penalties for rejected variants. To evaluate the proposed algorithms a computational experiment has been carried. It is also shown that there exists a 1.618-competitive strategy for the analyzed online problem.

High performance real-time neural scheduler for ATM switches

Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time.

MATLAB-Based Real-time Framework for Distributed Control Systems

Embedded systems are computer-based systems that often must have deterministic temporal behaviour. The application software must ensure overall system performance in terms of hard real-time constraints, reliability and safety requirements. Often application constraints include distribution of input/output. In some other cases, distribution is needed to achieve demanding performance or dependability requirements. This paper presents the design and implementation of the so-called Real Time Framework (RTF) that consists of a general environment for the easy generation of distributed control software. RTF covers from the specification of the distributed system to automatic code generation. The design is based on the integration of well-known commercial software for control systems into a framework that extends its use to distributed systems using a fieldbus as communication system. The internal design includes a model of the system in each design phase and information consistency is assured through an internal database.