Hard Real-time Computer Research Articles

Sampling-based Rig Conversion into Non-rigid Helper Bones

While 3D animation packages provide a wide variety of animation rigs for creating expressive skin animation, most interactive systems employ linear blend skinning for hard realtime computation. We propose a method for converting an arbitrary skeleton-driven deformer into a linear blend skinning-based helper bone rig. Our system builds the target rig by applying an example-based skinning technique that uses a minimal training dataset obtained from the source model by two-pass sampling of the skin deformation. The first uniform sampling analyzes the relationship between the rotation of each joint and the deformation of skin vertices. The second sampling composes a minimum training dataset by selecting important pose samples using novel geometrical measures. We also propose a skinning decomposition with similarity transformation algorithm for accurately approximating the non-rigid skin deformation behavior by helper bone transformations. Our experimental results demonstrate the proposed automated rig conversion into non-rigid helper bones from several skeleton-driven deformers, including Delta Mush deformers, corrective blendshapes, and virtual-muscle systems.

Designing a time predictable memory hierarchy for single-path code

Trustable Worst-Case Execution-Time (WCET) bounds are a necessary component for the construction and verification of hard real-time computer systems. Deriving such bounds for contemporary hardware/software systems is a complex task. The single-path conversion overcomes this difficulty by transforming all unpredictable branch alternatives in the code to a sequential code structure with a single execution trace. However, the simpler code structure and analysis of single-path code comes at the cost of a longer execution time. In this paper we address the problem of the execu- tion performance of single-path code. We propose a new instuction-prefetch scheme and cache organization that uti- lize the \knowledge of the future" properties of single-path code to reduce the main memory access latency and the number of cache misses, thus speeding up the execution of single-path programs.

An Introduction to Time-Constrained Automata

We present time-constrained automata (TCA), a model for hard real-time computation in which agents behaviors are modeled by automata and constrained by time intervals. TCA actions can have multiple start time and deadlines, can be aperiodic, and are selected dynamically following a graph, the time-constrained automaton. This allows expressing much more precise time constraints than classical periodic or sporadic model, while preserving the ease of scheduling and analysis. We provide some properties of this model as well as their scheduling semantics. We show that TCA can be automatically derived from source-code, and optimally scheduled on single processors using a variant of EDF. We explain how time constraints can be used to guarantee communication determinism by construction, and to study when possible agent interactions happen.

Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems

Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements. In particular, the emerging applications of Micro Electro-Mechanical Systems (MEMS) sensors, and their increasing integration, presents a challenging requirement to embed ultra-low power digital control architectures for these lithographically formed micro-structures. Controlling electromechanical structures of such a small scale, using naive digital controllers, can be prohibitively expensive (both in power and cost for portable or battery operated applications). In this paper, we describe the potential for control systems to be transformed into a set of co-operating parallel linear systems and demonstrate, for the first time, that this parallelization can reduce the total number of instructions executed, thereby reducing power, at the expense of controlled loss in control fidelity. Since the error tolerance of linear feedback control systems is mathematically well posed, this technique opens up a new, independent dimension for system optimization. We present a novel Computer-Aided Design (CAD) method to evaluate control fidelity, with varying timescales on the controller, and analyze the trade-off between performance and power dissipation. A CAD Metric for control fidelity is proposed and we demonstrate the potential for power savings using this decomposition on three different control problems.

Suboptimal Hybrid Model Predictive Control: Application to Sewer Networks

This paper presents an application of the suboptimal hybrid model predictive control (HMPC) algorithm previously proposed by the authors to large scale sewer networks. HMPC relies on the on-line solution of mixed integer programs (MIP) that are known to be NP-complete and whose worst case complexity scales exponentially with problem size. Modern MIP solvers are on the other hand highly efficient at taking advantage of problem structure and usually achieve average optimization times that are much better than the worst case predicts. But as the MIP constraints depend on the current state of the plant, complexity can vary considerably and unpredictable behavior can occur. To circumvent unpredictability and to be able to enforce hard real-time computation constraints, the number of feasible nodes in the MIP problem is limited online by adding constraints to the number of possible mode sequences over the prediction horizon. It is shown that in realistic scenarios concerning control of large scale sewer networks, depending on the value of parameters related to the mode sequence constraints (MSC), drastic reductions can be achieved in optimization time. Practical issues of the approach are also addressed.

Scheduling Hard and Soft Real-Time Communication in the Controller Area Network (CAN)

The paper introduces a mechanism to implement distributed scheduling for CAN-bus resource in order to meet the requirements of a dynamic distributed real-time system. The key issues considered here, are multicasting, distinguishing between hard real-time, soft real-time, and non real-time constraints, achieving high resource utilization for CAN-bus, and supporting dynamic hard real-time computing by allowing dynamic reservation of communication resources.

Language and compiler supported timing analysis in real-time control

To ensure temporally predictable execution behaviour of an embedded hard real-time computer control system, layer-by-layer predictability of the system must be provided. Based on a simple structured programming language, a programming environment for hard real-time applications is under construction designed to function temporally predictably, and to support an experimental hardware platform as well as a corresponding operating system. A compiler with an integrated analyser for execution-time analysis of tasks is used to determine usable, realistic and not too pessimistic run-time estimates.

An architecture supporting hard real-time computing

Efforts to develop a real-time computing architecture based on a deadline-driven dataflow machine and the hardware implementation of the architecture as a network of resource-adequate simple processors (S-processors) are described. This is done on two levels of abstraction: First, the architecture is presented as a whole, using the dataflow paradigm and a high-level visual language to describe the structure and the principle of implementation-detail-free programming. Secondly, on a technical level, the design of a single S-processor is given, including its reduced instruction set, which allows for a complete and convenient implementation of real-time algorithms, especially in distributed systems, without losing operational determinism. In a third step, the gap between the two levels of abstraction is closed by mapping the dataflow functions onto the S-processor's instruction set. The advantage of a real-time system based on the resource-adequate S-processor architecture is that it is simple enough for proper validation, but allows the implementation of real-time algorithms without any limitations. In the limit of one single process per processor it requires that each dataflow graph is analysed for realisability, which means that no effort is to be spent on analysing the schedulability for temporal correctness.

A Dynamic Scheduling Algorithm for Sporadic Tasks under Resource and Timing Constraints

Currently, we are developing a scheduler for hard real-time computer systems. The system of interest is a uniprocessor machine that supports the operating system and the application software composed of tasks that may be periodic or non-periodic (sporadic). All the tasks are said to be hard because they have strict timing requirements that must not be violated under any circumstances. Tasks may interact with each other by sharing critical resources. The problem is to sequence the tasks such that in all cases it is guaranteed that each task completes execution before its deadline and each resource is never accessed by more than one task simultaneously. We present a scheduling scheme that permits to solve this problem by using the Dynamic Priority Ceiling Protocol.