Hard IP Cores Research Articles

Формирование библиотек СФ-блоков в маршруте проектирования пользователь-ских схем на ПЛИС и РСнК

Intellectual Property (IP) cores are developed and used to accelerate the custom integrated circuits design flow and improve their final characteristics. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed in-terconnects while soft IP-cores can be synthesized from logic elements and should be placed and routed. To use IP-cores in automated design flow of integrated circuits on FPGA and RSoC it is necessary to develop IP-core libraries that allow identifying blocks on every stage of flow. This work shows the various soft and hard IP-core libraries’ types and formats used as a part of design flow for Russian FPGA and RSoC. It describes the methods of designing libraries needed by CAD systems at the stages of logic synthesis, automatic technological mapping and layout synthesis. Also, it considers soft and hard IP-core libraries’ distinct features and the methods of their formation adjusted for the FPGA and RSoC architecture. The design methods have been proposed that allow designing of libraries necessary for automated implementation of hard as well as soft IP-cores using advantage of base FPGA and RSoC architecture.

Core Communication Interface for FPGAs

The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP cores replacement during the FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.

A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic

Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding structure, which refers to improved decoding, input reduction, and simulated annealing inputs swapping approaches. Furthermore, utilizing similar multilevel decoding logic as the responses verifier, a novel cost-efficient input vector monitoring concurrent on-line BIST scheme is presented. The proposed scheme is applicable to the concurrent on-line testing for the CUT, the detail of which can not be obtained, such as hard IP cores. Experimental results indicate that the proposed optimization approaches can significantly reduce the hardware overhead of the decoding structure, and the proposed scheme costs lower hardware than other existing schemes.

Secure event logging in sensor networks

Health care applications based on sensors are gaining popularity. In wireless body area networks (WBANs), sensing data are gathered from a set of nodes deployed on the patient’s body and sent to a central server. In such environments, security and privacy must be top priorities. Moreover, since decision-making is performed on the basis of the collected data, it can be important to maintain the chronological order of events in a secure way. In view of this, this paper proposes a system for secure logging of events in sensor networks by gathering in a secure and reliable way all information at one central point. The system guarantees the chronological order of logged events sent by the different sensors. It also allows one to detect the modification, deletion, and addition of logged data. As a proof of concept, we have designed a prototype of the gateway sensor on an FPGA platform that is responsible for the secure logging and the secure transmission of this information. Our prototype is based on the low-cost Spartan-6 FPGA which is equipped with several hard IP-cores such as Ethernet and CompactFlash, which makes it suitable for event storage. As it turns out, the FPGA board (SP-605) is able to store 20,830 logged events, computes digests in 2.51 μs and only uses 56% of the LUTs of the FPGA. Thus, the reconfigurable nature of FPGAs makes them suitable for use in extending the capabilities of commercial gateways, in order to provide secure logging in a WSN.

Experience with a Hybrid Processor: K-Means Clustering

We discuss hardware/software co-processing on a hybrid processor for a compute- and data-intensive multispectral imaging algorithm, k-means clustering. The experiments are performed on two models of the Altera Excalibur board, the first using the soft IP core 32-bit NIOS 1.1 RISC processor, and the second with the hard IP core ARM processor. In our experiments, we compare performance of the sequential k-means algorithm with three different accelerated versions. We consider granularity and synchronization issues when mapping an algorithm to a hybrid processor. Our results show that speedup of 11.8X is achieved by migrating computation to the Excalibur ARM hardware/software as compared to software only on a Gigahertz Pentium III. Speedup on the Excalibur NIOS is limited by the communication cost of transferring data from external memory through the processor to the customized circuits. This limitation is overcome on the Excalibur ARM, in which dual-port memories, accessible to both the processor and configurable logic, have the biggest performance impact of all the techniques studied.