Формирование библиотек СФ-блоков в маршруте проектирования пользователь-ских схем на ПЛИС и РСнК

Abstract

Intellectual Property (IP) cores are developed and used to accelerate the custom integrated circuits design flow and improve their final characteristics. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed in-terconnects while soft IP-cores can be synthesized from logic elements and should be placed and routed. To use IP-cores in automated design flow of integrated circuits on FPGA and RSoC it is necessary to develop IP-core libraries that allow identifying blocks on every stage of flow. This work shows the various soft and hard IP-core libraries’ types and formats used as a part of design flow for Russian FPGA and RSoC. It describes the methods of designing libraries needed by CAD systems at the stages of logic synthesis, automatic technological mapping and layout synthesis. Also, it considers soft and hard IP-core libraries’ distinct features and the methods of their formation adjusted for the FPGA and RSoC architecture. The design methods have been proposed that allow designing of libraries necessary for automated implementation of hard as well as soft IP-cores using advantage of base FPGA and RSoC architecture.