Hard Intellectual Property Research Articles

Constant delay systolic binary counter with variable size cellular automaton based prescaler

An One-Dimension (1D) Cellular Automaton (CA) is studied as a generator for the radix-2 sequence, presenting suitable characteristics for the design of a fast and constant delay synchronous digital counter. The main contribution of this work is the proposal of a new type of synchronous digital counters including a CA-based prescaler and consecutive counting modules of various configurations (in terms of bitlength, speed and area requirements) to result in a modular and systolic counting structure with the minimum redundant hardware and low-power operation. It is the first time that a thorough exploration of the 1D CA rule 102 is offered and considered as the prescaler of a systolic counter of heterogeneous modules in size, achieving the desired constant delay characteristic with low area/power penalty. The proposed counter, compared to hard Intellectual Property (IP) cores, presents up to 90% enhancement of speed for 9.37%–33.0% area penalty for reconfigurable technologies.

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou. For the first time, we leverage the 2.5D interposer technology to establish system-level security in the face of hardware- and software-centric adversaries. More specifically, we integrate chiplets (i.e., third-party hard intellectual property of complex functionality, like microprocessors) using a security-enforcing interposer. Such hardware organization provides a robust 2.5D root of trust for trustworthy, yet powerful and flexible, computation systems. The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. The system-level activities of all untrusted commodity chiplets are checked continuously against security policies via physically separated security features. Aside from the security promises, the good economics of outsourced supply chains are still maintained; the system vendor is free to procure chiplets from the open market, while only producing the interposer and assembling the 2.5D system oneself. We showcase our scheme using the Cortex-M0 core and the AHB-Lite bus by ARM, building a secure 64-core system with shared memories. We evaluate our scheme through hardware simulation, considering different threat scenarios. Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust.

Transformable Electronics Implantation in ROM for Anti-Reverse Engineering

The protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. Read Only Memories (ROMs) serve as important non-volatile memory in various hardware systems to store predefined data and programs, which is critical to IP protection. Its pre-determined layout pattern makes unauthorized data extraction through chip-level reverse engineering easy to carry out. Advanced reverse engineering techniques can physically disassemble the chip and derive the IPs precisely at a much lower cost than the value of IP design that chips carry. This invasive hardware attack obtaining information from IC chips always violates the IP rights of vendors. This paper proposes a new security mechanism implanted ROM design to address the vulnerability to reverse energy attacks. Irreversible via in ROM layout transform triggered by reverse engineering completely changes the electrical properties and the physical structure of ROMs that determine the stored data. Newly-created patten will significantly increase the difficulty of reverse engineering, even lead the attackers to another working function mode. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Two widely used ROM scheme cases have been studied to test the design method and its effectiveness. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead. CCS Concepts: Security and privacy → Hardware reverse engineering; Hardware → Hard and soft IP

Self-triggering hardware trojan: Due to NBTI related aging in 3-D ICs

3-D ICs provide more transistor density and higher performance at smaller area compared to traditional 2-D ICs. However, elevated temperatures and longer heat dissipation paths in 3-D IC can lead to non-ideal delay variations. Higher temperatures lead to negative bias temperature instability (NBTI), and consequently shifts threshold voltage (Vth), which leads to current degradation and delay increment. These variations can be exploited by hardware intruder and introduce malicious circuit components causing malfunctioning in 3-D ICs. This paper takes the threat model in which the attacker has access to the hard-intellectual property (IP) development, and defender is at the foundry. This paper demonstrates that a hardware intruder can leverage the exacerbated NBTI effect to trigger the Trojan payload. Consequently, such Trojans does not require a conventional triggering circuit; hence we named it as self-triggered. The proposed hardware Trojan is very difficult to detect and can scape various countermeasures at testing phase due to ‘non-existing triggering signal’. The point of attack for the proposed Trojan is the body of the semiconductor device, for example, the body of PMOS device. When the Trojan gets activated it shorts the body and source of the PMOS to ground leading the device without power supply. We discussed the stealthy nature of our proposed Trojan against the existing countermeasures and also provided a discussion on a novel avenue of detecting such kinds of hardware Trojans.

The Flow of Knowledge from the Academic Research Base into the Economy: The Use and Effectiveness of Formal IPRs and 'Soft IP' in UK Universities

Academics produce a wide range of intellectual property (IP) products, which can be transferred to industry, government and other external stakeholders in different ways. Models of IP transfer involve different roles played by technology transfer offices, scientists, external commercialisation companies and universities themselves. Two comprehensive literature reviews recently commissioned by the Strategic Advisory Board for Intellectual Property Policy (SABIP) (Baghurst et al, 2009; Rogers et al, 2009) have emphasised that different models of IP transfer can be appropriate in different circumstances. They stressed the need for more extensive investigation into the nature, advantages, value and limitations of “soft” forms of intellectual property (IP) – such as copyright, open source, trademarks and design rights – in counterbalancing the predominant use of patents (or “hard IP”). Such research would provide a more complete picture of the full contribution made by university knowledge to industry and society. Our report makes an original contribution to the understanding of different IP governance models of university-industry knowledge transfer. It also offers new analysis of the absolute and relative importance of “hard” and “soft” IP in the knowledge flows between universities and external stakeholders. Our focus is on processes of direct and indirect knowledge transfer from university to industry, government and society, and on their feedback to universities through knowledge and financial flows.

Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection

Unlike conventional legal means, digital watermark enables an effective self-protection mechanism for Very Large Scale Integration (VLSI) designers to protect their intellectual property (IP). However, existing watermarking techniques come with unpredictable and often high design and performance overhead, which makes them impractical. In this paper, we propose an ultra-low overhead watermarking scheme to protect hard IPs, the dominating form of commercial IPs. Our approach is based on the observation that an optimized scan design uses two complementary connections between two adjacent scan cells. Such scan design flexibility in the selection of local connection styles provides a vehicle to embed watermarking constraints. It can conveniently be implemented by local rewiring and/or introducing dummy scan cells. The test vectors will be changed accordingly to reflect the watermarked connection styles in order to guarantee the test coverage. This approach offers two unique features: 1) ultra-low overhead and 2) easy detectability. First, because the scan chain order is maintained and these changes are local, the proposed watermarking technique will introduce ultra-low overhead in terms of area, power, and speed. Next, watermark can be extracted from the test vectors and/or the corresponding scan output. Experimental results validate that the performance overhead is negligible (almost zero on the most cases) and the watermark is resilient to various possible attacks.

Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification

A manufacture-ready layout is vulnerable to misappropriation when it is either fabricated as a chip in a fabrication facility, or reused in a system-on-chip house. We propose an intellectual property protection (IPP) scheme IPP_MRL for protection of m anufacture- r eady l ayout against unauthorized reuse and inclusion of Trojans. The IPP_MRL inserts watermarks in the layout according to designer’s signature with an effect of tuning the delays at selected scan flip-flops. Certain dummy fills are reoriented in the neighborhood of selected net segments and it causes fine tuning of delay; certain other selected net segments are resized for coarse change in delay. The IPP_MRL not only verifies the watermark in the layout, but also captures its effect as delay fault-induced responses from the packaged chips, fabricated from the watermarked layout, by applying a faster test clock. Due to the controlled effect of watermarking on delay, responses are resilient against process and temperature variation, but capable of detecting hardware Trojan. The method is adaptive to device aging. The results for ISCAS’85 and ISCAS’89 benchmark circuits show that the overhead of watermarking on circuit delay is less than 0.05% and the probability of true false or false true can be at most $\sim 10^{-6}$ .

Socially Rivalrous Information: Of Candles, Code, and Virtue

This article presents a novel historical and philosophical critique of the prevailing view among intellectual property theorists that is best modeled as a non-rival economic resource. The article traces the prevailing view about back to the philosophers and scientists whose thought dominated the Eighteenth Century Enlightenment - particularly Francis Bacon, Isaac Newton, and John Locke. In fact, one of the enduring metaphors for the non-rival of - Thomas Jefferson's candle - depends on a view of nature drawn directly from Bacon, Newton and Locke. It is surprising that this metaphor endures. Contrary to the Enlightenment project, the epistemology and ontology that informs the notions of cyberspace and the information commons are non-foundationalist and constructivist. Indeed, the predominant postmodern critique of intellectual property revolves around the social construction of the romantic author. This paper demonstrates, however, that Claude Shannon's mathematical theory fuels the trope that is a sort of that can be abstracted from any context and freely shared without diminution. The aphorism code is law, then, represents a curious mix of Enlightenment and postmodern thought. This mix does not work well. It leads to a groundless pragmatism pitted with intractable empirical lacunae. The article proposes instead a critical realist perspective on the socially rivalrous aspects of information. This perspective recognizes that has a real relation to an external reality and yet, at the same time, that is both socially constructed and a tool of social construction. The paper demonstrates that the law recognizes how plays precisely such a community-constructive role in areas outside hard intellectual property law and cyberlaw. In particular, the law of trade secrets, insider trading, and pre-contract disclosures regulates the socially rivalrous aspects of information. The article then suggests that policy should attend to virtues and practices that enhance human flourishing in communities constructed by rivalrous information, using the network neutrality debate as an example.

Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture

The increasing gap between design productivity and chip complexity and the emerging systems-on-chip (SoCs) architectural template have led to the wide utilization of reusable hard intellectual property (IP) cores. Macro block-based physical design implementation needs to find a well-balanced solution among chip area, on-chip communication energy, and critical communication path delay. We present in this paper an automated way to implement an energy optimal netlist interconnecting the hard macro blocks using a heavily segmented communication architecture. We explore the entire tradeoff curve among the network energy, chip area, and critical communication path delay at the floorplanning stage based on two real-life application drivers. Large energy gains with small area overheads are illustrated during the floorplanning stage. This tradeoff profile is a good guideline for the SOC designers to choose the optimal solution for their specific systems.

Calligrapher: a new layout-migration engine for hard intellectual property libraries

Modern systems-on-a-chip depend heavily on hard intellectual properties, such as standard cell and datapath libraries. As the foundries accelerate their update of advanced processes with increasingly complex design rules, and the libraries grow in flexibility and size, the cost of library development becomes prohibitively high. Automated layout-migration techniques used today, which are based on layout compaction developed a decade ago, corrupt advanced design considerations by honoring only design rules, and cannot cope with some of the new challenges involved. In this paper, we present a new integer linear programming (ILP)-based layout-migration engine, called calligrapher, and make the following contributions. First, we extend the recently proposed minimum perturbation (MP) metric designed to retain original layout design intentions, while overcoming its shortcoming of biased treatment of layout objects. Second, we propose a new design-rule-constraint algorithm, and prove its linear complexity for the number of constraints generated. Compared with what has been achieved in the literature, the proposed algorithm can significantly reduce the ILP solver time by limiting the constraint size. Third, we propose an iterative migration framework based on the concept of soft constraint. With this framework, two-dimensional compaction quality can be achieved with a runtime comparable to one-dimensional compaction. We demonstrate the effectiveness of calligrapher by migrating the Berkeley low-power libraries, originally developed for the 1.2-/spl mu/m MOSIS process, into TSMC 0.25- and 0.18-/spl mu/m technologies. We show that even for a very compact layout, our metric and the MP metric can make a difference by as much as 20%-45%. We also show that our iterative algorithm can improve the area by 10% on average compared to the traditional technique using the MP metric, and inflates the area by merely 7.5% compared to the traditional technique using minimum-area metric.

Set-top box system-on-chip design methodology

Reviews how the methodology for semiconductor intellectual property (IP) reuse for system-on-chip (SoC) designs has evolved from its first introduction. It has gone from an approach based largely on IP reuse to a state of-the-art design flow based on soft and hard IP blocks and floorplanning tools. This flow will be illustrated in one complex SoC present in the broadband communication market today, which is a set-top box IC containing a proprietary 64-bit processor and some general-purpose blocks, along with dedicated functions specifically designed by STMicroelectronics. Management of a design of this SoCs complexity is based on a top-down, block-based design style, including automatic floorplanning. This design style makes use of the classic divide-and-conquer strategy and enables a concurrent development process, guaranteeing timing convergence and correct chip assembly.

A LOW-POWER PARAMETERIZED HARDWARE DESIGN FOR THE ONE-DIMENSIONAL DISCRETE FOURIER TRANSFORM OF VARIABLE LENGTHS

This paper presents a new low-power parameterized hardware design for the one-dimensional (1D) discrete Fourier transform (DFT) of variable lengths. By combining the cyclic convolution formulation, block-based distributed arithmetic (BDA), and Cooley–Tukey decomposition algorithm together, we have developed a parameterized hardware design for the DFT of variable lengths ranging from 256 to 4096 points and with different modes of performance. The proposed design can perform different lengths of DFT computation through the configuration of parameters, which not only provides the flexibility in computing different length DFT but also facilitates the performance-driven design considerations in terms of power consumption and processing speeds, that is, we can configure the proposed design in different modes of performance by setting different parameters. This feature is beneficial to developing a parameterized DFT soft Intellectual Property (IP) core or hard IP core for meeting the system requirements of different silicon-on-a-chip (SOC) applications as compared with the existing fixed length DFT designs.