Hard-decision Decoding Research Articles

Progressive Algebraic Soft-Decision Decoding of Reed-Solomon Codes

The algebraic soft-decision decoding (ASD) algorithm is a polynomial-time soft decoding algorithm for Reed-Solomon (RS) codes. It outperforms both the algebraic hard-decision decoding (AHD) and the conventional unique decoding algorithms, but with a high computational cost. This paper proposes a progressive ASD (PASD) algorithm that enables the conventional ASD algorithm to perform decoding with an adjustable designed factorization output list size (OLS). The OLS is enlarged progressively leading to an incremental computation for the interpolation and an enhanced error-correction capability. Multiple factorizations are performed in order to find out the intended message polynomial which will be validated by a cyclic redundant check (CRC) code. The incremental interpolation constraints are introduced to characterize the progressive decoding. The validity analysis of the algorithm shows the PASD algorithm is a natural and computationally saving generalization of the ASD algorithm, delivering the same interpolation solution. The average decoding complexity of the algorithm is further theoretically characterized, revealing its dependence on the channel condition. The simulation results further validate the analysis by showing that the average decoding complexity can be converged to the minimal level in a good channel condition. Finally, performance evaluation shows the PASD algorithm preserves the error-correction capability of the ASD algorithm.

Packet Error Outage for Coded Systems Experiencing Fast Fading and Shadowing

In this paper, we consider the performance of coded wireless communication systems experiencing non-frequency selective fading channels in shadowed environments. The quality of service (QoS) in a wireless network is dependent on the packet error outage (PEO). We address the problem of finding a tractable expression for the coded PEO over Nakagami-m channels with shadowing, considering multilevel modulations, various block and convolutional channel coding schemes and hard decision decoding. In order to obtain the coded PEO, an inversion of the coded packet error probability (PEP) w.r.t. the signal to noise ratio (SNR) is needed. To this end, we propose an invertible approximation for the coded PEP w.r.t. the uncoded bit error probability (BEP) in Nakagami-m fading channels which is accurate for all BEPs of interest. The BEP itself depends on the average SNR and we hence make use of previous results on the inversion of the uncoded BEP w.r.t. the SNR in Nakagami-m fading channels, holding for M-PSK and M-QAM signals. We were thus able to obtain a reliable closed form expression for the coded PEO in flat fading and shadowing channels. The theoretical findings are verified by means of simulations.

Long Irregular LDPC coded OFDM with Soft Decision

OFDM with quadrature amplitude modulation (QAM) technique can be used for high speed optical applications. Increasing the order of modulation, the bit error rate (BER) increases. Forward Error correction (FEC) coding like LDPC coding is generally used to improve the BER performance. LDPC provides large minimum distance and also the power efficiency of the LDPC code increases significantly with the code length. In this paper we have compared the Soft decision and Hard decision algorithms of LDPC codes. A long Irregular LDPC code is simulated over the BIAWGN channel demonstrating the fact that LDPC coded OFDM with soft decision decoding provides very lower bit error rate as well as a larger gain in transmitter power and thus making the link more power efficient than the case with hard decision decoding. Through simulation, we have shown the advantages of using this long Irregular LDPC coded OFDM link in Optical wireless communication (OWC).

VHDL Design and FPGA Implementation of a Fully Parallel Architecture for Iterative Decoder of Majority Logic Codes for High Data Rate Applications

In this work, we propose a design and FPGA (Field Programmable Gate Arrays) implementation of three parallel architectures for majority logic decoder of low complexity for high data rate applications. These architectures are hard decision decoder architecture (Hard in - Hard out (HIHO)), the SIHO threshold decoding (Soft in – Hard out) and the SISO threshold decoding (Soft in – Soft out). The chosen code is the Difference Set Cyclic DSC code. The VHDL (Very high speed integrated circuit Hardware Description Language) design and the synthesis of such architectures show that such decoders can achieve high data rate with low complexity. In our case, the iterative decoder associated to the fully parallel SISO threshold decoders allows achieving high data rates, 2 clock cycles for two iterations with a complexity of 7350LEs.

A Simple Decoding Scheme for a Balanced 6/8 Modulation Code

Two-dimensional (2D) inter-symbol interference (ISI) and inter-page interference (IPI) are major concerns of holographic data storage (HDS). These problems can be mitigated by modulation code. A 6/8 balanced code is one of the modulation codes that has a 1:1 ratio of symbol “1” and symbol “0”. It avoids the IPI and has a low-pass filtering effect to reduce the ISI. However, the soft-decision decoding for a 6/8 balanced code needs many multiplications to calculate the Euclidean distances, making the circuit complicated. Hard-decision decoding is much simpler but does not perform as well as soft-decision decoding. Therefore, we propose a simple decoding scheme for a 6/8 balanced code which uses hard-decision decoding but performs almost as well as soft-decision decoding.

Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction

Reed-Solomon (RS) codes are widely used as forward correction codes (FEC) in digital communication and storage systems. Correcting random errors of RS codes have been extensively studied in both academia and industry. However, for burst-error correction, the research is still quite limited due to its ultra high computation complexity. In this brief, starting from a recent theoretical work, a low-complexity reformulated inversionless burst-error correcting (RiBC) algorithm is developed for practical applications. Then, based on the proposed algorithm, a unified VLSI architecture that is capable of correcting burst errors, as well as random errors and erasures, is firstly presented for multi-mode decoding requirements. This new architecture is denoted as unified hybrid decoding (UHD) architecture. It will be shown that, being the first RS decoder owning enhanced burst-error correcting capability, it can achieve significantly improved error correcting capability than traditional hard-decision decoding (HDD) design.

Enhancing the Error-correcting Capability of Imai-Kamiyanagi Codes for Data Storage Systems by Adopting Iterative Decoding using a Parity Check Tree

A novel low-complexity, soft decision technique which allows the decoding of distance-5 double error-correcting Imai-Kamiyanagi codes by using a parity check tree associated with the Tanner graph is proposed. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. For the AWGN channel, gains in excess of 1.5 dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (46, 32), (81, 64), and (148, 128) shortened Imai-Kamiyanagi codes.

An Investigation of Block Coding for Laplacian Noise

In many communication channels, the ambient disturbance is known through experimental evidence as well as theoretical considerations to deviate strongly from the Gaussian model. In order to evaluate the performance of digital signaling in such channels, the non-Gaussian noise must be properly modeled. The Laplace distribution is used here to model the non-Gaussian noise and study the performance of communication systems employing block data transmission in the presence of impulsive noise. Analytical expressions for assessing codeword error probability and bit error probability are derived for hard-decision decoders, soft-decision decoders and optimum maximum likelihood detectors in both nonfading and quasi-static Rayleigh fading scenarios. Numerical results are presented for different codes, block sizes and error rate levels. The characteristics of error performance are discussed for both nonfading and quasi-static Rayleigh fading channels.

Design of Low Complexity Non-Binary LDPC Codes with an Approximated Performance-Complexity Tradeoff

By presenting an approximated performance-complexity tradeoff (PCT) algorithm, a low-complexity non-binary low density parity check (LDPC) code over q-ary-input symmetric-output channel is designed in this manuscript which converges faster than the threshold-optimized non-binary LDPC codes in the low error rate regime. We examine our algorithm by both hard and soft decision decoders. Moreover, simulation shows that the approximated PCT algorithm has accelerated the convergence process by 30% regarding the number of the decoding iterations.

Design of a Merged Algorithm for Luby Transform Decoder

Luby transform exhibits near-optimal performance over Binary Erasure channel. However, on AWGN channel, Luby decoding technique suffers from error propagation. Consequently, a soft decoding strategy -Belief Propagation- similar to the LDPC has been adopted. In this strategy, the check node equation complexity is still a persistent problem affecting hardware implementation in terms of speed and area. We propose a decoding scheme that uses both Luby decoding technique and the soft input available at the receiver to reduce the check node equation complexity. In the proposed algorithm, error propagation has been mitigated thus reducing the signal-to-noise ratio significantly. Index Terms—Belief propagation, hard decision decoding, Luby transform codes, soft decision decoding, sum product algorithm

Efficient Information Set Decoding Based on Genetic Algorithms

In this paper, we describe a hard-decision decoding technique based on Genetic Algorithms (HDGA), which is applicable to the general case of error correcting codes where the only known structure is given by the generating matrix G. Then we present a new soft-decision decoding based on HDGA and the Chase algorithm (SDGA). The performance of some binary and non-binary Linear Block Codes are given for HDGA and SDGA over Gaussian and Rayleigh channels. The performances show that the HDGA decoder has the same performances as the Berlekamp-Massey Algorithm (BMA) in various transmission channels. On the other hand, the performances of SDGA are equivalent to soft-decision decoding using Chase algorithm and BMA (Chase-BMA). The complexity of decoders proposed is also discussed and compared to those of other decoders.

Fast Chase Decoding Algorithms and Architectures for Reed–Solomon Codes

Chase decoding is a prevalent soft-decision decoding method for algebraic codes where an efficient bounded-distance decoder is available. Essentially, it repeatedly applies bounded-distance decoding upon combinatorially flipping certain least reliable bits (or patterns for nonbinary case). In this paper, we devise a one-pass Chase decoding algorithm of Reed-Solomon codes such that the desired error locator polynomial by flipping an error pattern is obtained in one pass (when operated in parallel) through utilizing the preceding results. This is effectively achieved through cumulative interpolation and linear-feedback-shift-register (LFSR) synthesis techniques. Furthermore, through converting the algorithm into the transform domain, exhaustive root search for each error locator polynomial is circumvented. Computationally, the new algorithm exhibits linear complexity , in attempting to determine a candidate codeword associated with each additionally flipped symbol/pattern; it compares favorably to quadratic complexity by straightforwardly utilizing hard-decision decoding, where and denote the code length and minimum distance, respectively. We also reveal a corrected algorithm for one-pass generalized minimum distance (GMD) decoding for Reed-Solomon codes from Koetter's original work. In addition, we devise a highly efficient one-pass Chase decoding algorithm for binary Bose-Chaudhuri-Hocquenghem (BCH) codes by taking advantage of a key characteristic of the Berlekamp algorithm. Finally, we present a systolic very large-scale integration (VLSI) decoder architecture through slightly compromising the proposed one-pass Chase decoding algorithm. It takes clock cycles to complete one iteration by flipping one error pattern. Both circuit and memory complexities are dictated by the dimension of flipping patterns; in particular, they are independent of the code length or the minimum distance , rendering it highly attractive for various applications.

A Novel Error-Correcting System Based on Product Codes for Future Magnetic Recording Channels

We propose a novel construction of product codes for high-density magnetic recording based on binary low-density parity check (LDPC) codes and binary image of Reed-Solomon (RS) codes. Moreover, two novel algorithms are proposed to decode the codes in the presence of AWGN errors and scattered hard errors (SHEs). Simulation results show that at a bit-error rate (BER) of approximately 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-8</sup> , our method allows improving the error performance by approximately 1.9 dB compared with that of a hard decision decoder of RS codes of the same length and code rate. For the mixed error channel, including random noise and SHEs, the signal-to-noise ratio is set at 5 dB, and 150 to 400 SHEs are randomly generated. The bit-error performance of the proposed product code shows a significant improvement over that of equivalent random LDPC codes or serial concatenation of LDPC and RS codes.

Performance of channel codes in wireless communication systems using efficient simulation

With the widespread of new radio systems, it is essential that their performance is evaluated prior to auxiliary design and commercial development. Although there are many methods to model and estimate the performance of a given radio system with some accuracy, most of these methods require high computational resources or long simulation times. In this study, the authors present a general and efficient simulation method for estimating the performance of a wireless communication systems, with particular emphasis for its forward error correction sub-system when using block channel codes, for channels affected by additive white Gaussian noise, free space attenuation, shadowing, fading and interfering sources. Both soft-decision (SD) and hard-decision (HD) decoding are considered and the overall performance takes into account modulation, coding and channel conditions. This efficient simulation is compared with the Monte Carlo simulation method and its performance is assessed for the Tomlinson, Cercas and Hughes code family. This new simulation method has an temporal efficiency of two or three orders of magnitude for SD and HD and three or four orders, considering a bit-error-ratio of 0.01 and 0.001%, respectively.

Application of energy efficient soft-decision error control in wireless sensor networks

Energy efficient reliable communication over an unpredictable wireless medium is a major challenge for resource constrained wireless sensor nodes in process/environment control application. In this paper, we propose a Soft Decision Decoding (SDD) based advanced Forward Error Correction (FEC) scheme for low power distributed sensor nodes. The proposed BCH (Bose-Chaudhuri-Hocquenghem) based adaptive Chase-2 decoding scheme offers attractive energy benefits as compared to Hard Decision Decoding (HDD). The reduced decoding complexity is obtained by limiting the codeword search space and fewer algebraic operations compared to standard Chase-2. A realistic environmental scenario incorporating path loss, Rayleigh fading and Additive White Gaussian Noise has been considered to investigate the performance of the proposed scheme. A detailed comparison is carried out with HDD of BCH codes using the widely known Crossbow MicaZ node parameters. The simulation results indicate that for low power WSN, the proposed SDD based adaptive scheme offers better tradeoff between energy and reliability than HDD schemes.

Decoding of the (31, 16, 7) quadratic residue code with four-error correcting capability

A high-speed algorithm for decoding the binary (31, 16, 7) quadratic residue (QR) code up to four errors is proposed. Core to the key idea lies in an innovative integration of the reliability-search procedure and the insight of the weight distribution of the code for searching the candidate codewords. Accordingly, the maximum-likelihood (ML) criterion is applied to pick the most possible codeword. Through simulation over the additive white Gaussian noise (AWGN) channel, it is concluded that the error-correcting performance of the new decoder is superior to that of a Chase-II decoder when no more than four errors occur. The overall bit error rate (BER) of the proposed decoder is close to that of the Chase-II decoder. More importantly, the new decoder results in great reductions of 72.34% and 92.37% in the signal-to-noise ratio (SNR) values of 0 and 7, respectively. The proposed algorithm suggests an alternative to enhance the error-correcting capability of the hard-decision decoder, but with a lower decoding complexity.

Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes

Generalized minimum distance (GMD) decoding of Reed---Solomon (RS) codes can correct more errors than conventional hard-decision decoding by running error-and-erasure decoding multiple times for different erasure patterns. The latency of the GMD decoding can be reduced by the Kotter's one-pass decoding scheme. This scheme first carries out an error-only hard-decision decoding. Then all pairs of error-erasure locators and evaluators are derived iteratively in one run based on the result of the error-only decoding. In this paper, a more efficient interpolation-based one-pass GMD decoding scheme is studied. Applying the re-encoding and coordinate transformation, the result of erasure-only decoding can be directly derived. Then the locator and evaluator pairs for other erasure patterns are generated iteratively by applying interpolation. A simplified polynomial selection scheme is proposed to pass only one pair of locator and evaluator to successive decoding steps and a low-complexity parallel Chien search architecture is developed to implement this selection scheme. With the proposed polynomial selection architecture, the interpolation can run at the full speed to greatly increase the throughput. After efficient architectures and effective optimizations are employed, a generalized hardware complexity analysis is provided for the proposed interpolation-based decoder. For a (255, 239) RS code, the high-speed interpolation-based one-pass GMD decoder can achieve 53% higher throughput than the Kotter's decoder with slightly more hardware requirement. In terms of speed-over-area ratio, our design is 51% more efficient. In addition, compared to other soft-decision decoders, the high-speed interpolation-based GMD decoder can achieve better performance-complexity tradeoff.

High-Speed RS(255, 239) Decoder Based on LCC Decoding

Algebraic Soft-Decision Decoding (ASD) of Reed–Solomon (RS) codes provides higher coding gain over the conventional hard-decision decoding (HDD), but involves high computational complexity. Among the existing ASD methods, the Low Complexity Chase (LCC) decoding is the one with the lowest implementation cost. LCC decoding is based on generating 2 η test vectors, where η symbols are selected as the least reliable symbols for which hard-decision or the second more reliable decision are employed. Previous decoding algorithms for LCC decoders are based on interpolation and re-encoding techniques. On the other hand, HDD algorithms such as the Berlekamp–Massey (BM) algorithm or the Euclidean algorithm, despite of their low computational complexity, are not considered suitable for LCC decoding. In this paper, we present a new approach to LCC decoding based on one of these HDD algorithms, the inversion-less Berlekamp–Massey (iBM) algorithm, where the test vectors are selected for correction during decoding on occurrence of hard-decision decoding failure. The proposed architecture when applied to a RS(255, 239) code with η=3, saves a 20.5% and 2% of area compared to the LCC with factorization and a factorization-free decoder, respectively. In both cases, the latency is reduced by 34.5%, which is an increase of throughput rate in the same percentage since the critical path is the same in all the competing architectures. So an efficiency of at least 56% in terms of area-delay product can be obtained, compared with previous works. A complete RS(255, 239) LCC decoder with η=3 has been coded in VHDL and synthesized for implementation in Vitex-5 FPGA device, and by using SAED 90 nm standard cell library as well, and find a decoding rate of 710 Mbps and 4.2 Gbps and area of 2527 slices and 0.36 mm2, respectively.

Efficient Iterative Techniques for Soft Decision Decoding of Reed-Solomon Codes

Two new iterative soft decision decoding methods for Reed-Solomon (RS) codes are proposed. These methods are based on bit level belief propagation (BP) decoding. In order to make BP decoding effective for RS codes, we use an extended binary parity check matrix with a lower density and reduced number of 4-cycles compared to the original binary parity check matrix of the code. In the first proposed method, we take advantage of the cyclic structure of RS codes. Based on this property, we can apply the belief propagation algorithm on any cyclically shifted version of the received symbols with the same binary parity check matrix. For each shifted version of received symbols, the distribution of reliability values will change and deterministic errors can be avoided. This method results in considerable performance improvement of RS codes compared to hard decision decoding. The performance is also superior to some popular soft decision decoding methods. The second method is based on information correction in BP decoding. It means that we determine least reliable bits and by changing their channel information, the convergence of the decoder is improved. Compared to the first method, this method needs less BP iterations (less complexity) but its performance is not as good.

FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm

In this paper, a simplified message passing algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity. The algorithm is based on simple hard-decision decoding techniques while utilizing the advantages of soft channel information to improve decoder performance. It has been validated through simulation using LDPC code compliant with Wireless Local Area Network (WLAN – IEEE 802.11n) standard. The results show that theproposed algorithm can achieve significant improvement in bit error rate (BER) performance and average decoding iterations compared to fully hard-decision based decoding algorithms. The proposed algorithm has been implemented and tested on Xilinx Virtex 5 FPGA. With significantly reduced hardware resources, the implemented decoder can achieve an average throughput of ~16.2 Gbps with a BER performance of 10-5 at an Eb/No of 6.25 dB.