Handle Layer Research Articles

Fabrication and Characterization of Silicon (100) Membranes for a Multi-beam Superconducting Heterodyne Receiver

We fabricated silicon (100) membranes of 3 mm in diameter on the surface of silicon-on-insulator (SOI) substrates and investigated the characteristics of the membranes. The handle layer of one SOI substrate was etched using deep reactive ion etching process with the buried oxide (BOX) layer that remained together with the device layer. The BOX layer of the other SOI substrate was removed using C4F8-based plasma etching after the handle layer etching. The surfaces of both silicon (100) membranes were observed using the scanning white light interferometer system at room temperature. Both silicon (100) membranes have dome-like deformations. The silicon (100) membranes are effectively flattened by etching the BOX layer under the device layer. Both silicon (100) membranes were cooled from room temperature to 4 K by a Gifford–McMahon refrigerator. Wrinkles appeared on the surfaces of both silicon (100) membranes when the temperature dropped to about 200 K. However, the wrinkles disappeared below about 180 K. This phenomenon indicates the wrinkles at low temperature would depend on the properties of the silicon (100) of the device layers and independent of the properties of the BOX layers under the silicon (100) membranes.

Enhancement of vertical integration density by engineered BSOI wafers

The lateral and vertical integration density of bulk microelectromechanical systems (MEMS) using bonded silicon-on-insulator (BSOI) wafers is significantly enhanced if the handle wafer is used as an electrical redistribution layer. Therefore isolated conductive paths should be integrated in the handle wafer, which are connected to the surface of the BSOI-wafer by high aspect ratio contacts (VIAs) through the device layer of the BSOI-wafer. In the present study we report on a fabrication process for customer specific designed BSOI wafers with VIAs from the device to the handle layers. Wafer bonding, wafer edge shaping and thinning of the wafers, which are critical processes for the fabrication of the BSOI-wafers, are discussed. The contacts to the handle wafer through the 75 µm thick device layer are created by 10 µm wide and 75 µm deep trenches filled with highly doped n-type poly-silicon. From current–voltage measurements an ohmic behaviour of the contacts with a resistance of around 120 Ω is demonstrated.

Design and Verification of a Structure for Isolating Packaging Stress in SOI MEMS Devices

This paper proposes and verifies a structure for the isolation of packaging stress in silicon-on-insulator-based microelectromechanical systems devices. The packaging-stress isolation structure resides on the handle layer and consists of a circular disk, eight elastic beams, and a support frame. The disk is located in the center of the die and occupies less than 5% of the handle-layer area; this can reduce packaging stress and avoid uneven stress distribution. The elastic beams are L-shaped and symmetrically distributed to decouple the deformation from the disk to the frame and suppress the stress evenly. The in-plane and out-of-plane deformation induced by packaging stress was modeled and experimentally measured. The comparison results demonstrate that the packaging stress was successfully isolated.

Fabrication process for 200 nm-pitch polished freestanding ultrahigh aspect ratio gratings

A fully integrated fabrication process has been developed to fabricate freestanding, ultrahigh aspect ratio silicon gratings with potassium hydroxide (KOH)-polished sidewalls. The gratings are being developed for wavelength-dispersive, soft x-ray spectroscopy on future space telescopes. For this application, the grating needs to have a large open-area fraction and smooth sidewalls (roughness < 1 nm) to maximize efficiency. The prototype gratings fabricated with the process presented here have been tested on a synchrotron beamline and have demonstrated an absolute diffraction efficiency greater than 30% for 2 nm-wavelength x-rays in blazed orders. This efficiency is greater than twice the efficiency of previously fabricated gratings. The fabrication process utilizes silicon-on-insulator wafers where the grating and a cross support are etched in the device layer, and an additional structural support is etched in the handle layer. The device layer and handle layer are both etched via deep reactive-ion etching using a Bosch process. The buried SiO2 layer stops both etches and is removed at the end of the process to create a freestanding structure. The gratings have a pitch of 200 nm, a depth of 4 μm, and the bars are polished via KOH. The polishing process reduces both the roughness and the grating-bar thickness. The finished gratings span an area of approximately 10 by 30 mm, supported by 1 mm-wide hexagons in the handle layer.

Dicing‐free SOI process based on wet release technology

A simple, low-cost and reliable dicing-free silicon-on-insulator (SOI) process is presented for solving three major challenges in manufacturing the microelectromechanical systems devices, i.e. stiction, notching and dicing damage. In this process, the cavity is used and patterned on the handle layer to solve the stiction problem, and the exposed oxide is removed in hydrofluoric acid (HF) solution before deep reactive ion etching (DRIE) on the structure layer to eliminate the notching effect's impact. The dies are attached temporally to a designed frame by the silicon dioxide. After removing the oxide using HF solution, the dies are separated from the wafer cleanly without dicing damage. The layout design rules on the front side and backside patterns are established. Furthermore, a grooved carrier wafer with specific design rules was introduced to enhance the yield rate of the process. Finally, a tuning fork gyroscope was fabricated to demonstrate the proposed fabrication process and a yield rate of over 81% was achieved. The process solves the stiction, notching and dicing damage problems only involving the apparatus associated with lithography and DRIE, offering an economic and complete SOI process solution.

A Unique 3D Integration Approach for SOI Substrates - Mating Device Layer CVD W Filled Tsvs with Handle Layer ECD Cu Filled Tsvs

In recent years microelectronic packaging development has focused on 3D integration in order to compensate for the decrease in traditional Moore’s Law scaling. 3D integration allows increased I/O counts, lower RC time constants, lower power consumption, and better thermal sinking. Furthermore, 3D integration decreases areal density through stacking chips and connecting their electrical signals with through substrate vias (TSVs) as opposed to wire bonding. A significant amount of development has been achieved integrating TSVs with standard silicon (Si) substrates; however, very little development has been made integrating this technology with silicon-on-insulator (SOI) substrates1. Certain MEMS applications take advantage of the use of SOI wafers with relatively thick device layer silicon, however the integration of TSVs with these unique SOI substrates (e.g., 600um handle, 1um buried oxide, and 25um thick device layer) presents distinct challenges when making electrical connections through the device layer Si, buried oxide (BOX), and the handle Si. This is particularly true for cases in which the handle Si is not thinned. In this work, we present a novel TSV integration approach in which electrochemical deposition (ECD) is used to connect copper (Cu) vias, filled in the handle of the substrate, to tungsten (W) vias filled by chemical vapor deposition (CVD) in the device layer of a SOI substrate.Deep reactive ion etching (DRIE) has become the most accepted process for creating TSVs when working with semiconductor materials. After forming the vias, chemical vapor deposition, atomic layer deposition (ALD), and/or electrochemical deposition are used to deposit an insulating material for electrical isolation, a barrier layer to prevent diffusion, and a conductive material for electrical connection. CVD is typically used for all three of these purposes if the film thicknesses and aspect ratios are small enough and geometries are not overly complex. ALD is utilized for both the insulating layer and the diffusion barrier when CVD is not capable of conformally coating intricate geometries. ECD is used to fill the vias with a conductive material when via dimensions are too large for CVD, which is common in MEMS applications. This work will utilize DRIE for etching topside vias through the device layer Si and CVD for filling these vias with W. DRIE is also used for etching the handle Si and BOX layers using a hardmask on the backside of the substrate. Two approaches are investigated and presented for utilizing ECD to form Cu TSVs and connect the backside of the wafer to the W TSVs imbedded in the device layer of the SOI substrate. In both of these approaches, ALD is used to deposit a conformal layer of Al2O3 to isolate the TSVs from the handle Si. A spacer etch is performed to remove the Al2O3 from horizontal surfaces, revealing the W TSVs previously fabricated in the device layer Si. The first approach is to fill the TSVs with Cu from the bottom up, initiating plating from a seed layer deposited only at the bottom of the backside vias. This approach allows a conventional makeup chemistry to be used with sulfuric acid (H2SO4) as the electrolyte in conjunction with a periodic reverse plating regime. The second approach is to fill the vias from the outside in, initiating plating from a conformal platinum (Pt) seed layer deposited by ALD and using methanesulfonic acid (MSA), rather than H2SO4, as the makeup chemistry electrolyte2. The higher solubility of Cu in MSA (80g/L) compared to H2SO4 (50g/L) reduces mass transport limited depletion of Cu ions in the vias, leading to conformal Cu deposition throughout the depth of the vias. The advantages, disadvantages, and challenges associated with each of these two integration approaches will be presented.Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000. G-K. Lau, J. Soon, H-Y Li, K. Chui, and Y. Mingbin, “Process Integration and Challenges of Through Silicon Via (TSV) on Silicon-On-Insulator (SOI) Substrate for 3D Heterogeneous Applications.” 17th Electron. Packaging Tech. Conf., (2015). S. K. Cho, M. J. Kim, and J. J. Kim, “MSA as a Supporting Electrolyte in Copper Electroplating for Filling of Damascene Trenches and Through Silicon Vias.” Electrochemical and Solid-State Letters, 14 (5) D52-D56 (2011).

A new design and a fabrication approach to realize a high performance three axes capacitive MEMS accelerometer

This paper presents a new fabrication approach and design for a three axis capacitive MEMS accelerometer that is capable of measuring externally applied accelerations in three orthogonal axes. Individual lateral and vertical axis accelerometers are fabricated in the same die on an SOI wafer which is anodically bonded to a glass substrate. Handle layer of the SOI wafer is used as the top electrode for the vertical axis accelerometer. This accelerometer has a 2mm2 perforated electrode area anchored to the glass substrate by four beams. The lateral axis accelerometers on the other hand, have comb finger structures with a 2.7×4.2mm device size and anchored to the glass substrate by six folded beams. Rest capacitance of the vertical axis accelerometer is designed to be 8.8pF, and it is 10.2pF for the lateral axis accelerometers. The system level performance results are obtained using analog readout circuitry integrated to each axis separately. The x- and y-axis accelerometers show a noise floor and bias instability equal or better than 13.9μg/√Hz and 17μg, respectively, while the z-axis accelerometer shows 17.8μg/√Hz noise floor and 36μg bias instability values.

Practical multi-featured perfect absorber utilizing high conductivity silicon

We designed all-silicon, multi-featured band-selective perfect absorbing surfaces based on CMOS compatible processes. The center wavelength of the band-selective absorber can be varied between 2 and 22 μm while a bandwidth as high as 2.5 μm is demonstrated. We used a silicon-on-insulator (SOI) wafer which consists of n-type silicon (Si) device layer, silicon dioxide (SiO2) as buried oxide layer, and n-type Si handle layer. The center wavelength and bandwidth can be tuned by adjusting the conductivity of the Si device and handle layers as well as the thicknesses of the device and buried oxide layers. We demonstrate proof-of-concept absorber surfaces experimentally. Such absorber surfaces are easy to microfabricate because the absorbers do not require elaborate microfabrication steps such as patterning. Due to the structural simplicity, low-cost fabrication, wide spectrum range of operation, and band properties of the perfect absorber, the proposed multi-featured perfect absorber surfaces are promising for many applications. These include sensing devices, surface enhanced infrared absorption applications, solar cells, meta-materials, frequency selective sensors and modulators.

Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers

We have developed for the first time a 3-D integrated CMOS image sensor with pixel-parallel analog-to-digital converters (ADCs). Photodiode (PD) and inverter layers are prepared on separate silicon-on-insulator layers and directly bonded with damascened Au electrodes. The handle layer is then removed by grinding and XeF2 vapor phase etching to expose the PD surface. The developed process is suitable for pixelwise interconnection because it allows the damascened Au electrodes to be 1 $\mu \text{m}$ in diameter or less. An ADC circuit is designed based on pulse frequency modulation where pulses are generated proportional to the illumination intensity, and contains a PD, inverters, a reset transistor, and counters. A prototype 3-D integrated CMOS image sensor is also developed with 64 pixels, which acquires video images without pixel defects. A wide dynamic range of >80 dB is confirmed for the incident light intensity. The experimental results demonstrate the feasibility of pixel-level 3-D integration for high-performance CMOS image sensors.

A Bulk-Micromachined Three-Axis Capacitive MEMS Accelerometer on a Single Die

This paper presents a high-performance three-axis capacitive microelectromechanical system (MEMS) accelerometer implemented by fabricating individual lateral and vertical differential accelerometers in the same die. The fabrication process is based on the formation of a glass-silicon-glass multi-stack. First, a 35- $\mu \text{m}$ thick $\langle 111\rangle $ silicon structural layer of an Silicon-On-Insulator (SOI) wafer is patterned with deep reactive ion etching (DRIE) and attached on a base glass substrate with anodic bonding, whose handle layer is later removed. Next, the second glass wafer is placed on the top of the structure not only for allowing to implement a top electrode for the vertical accelerometer, but also for acting as an inherent cap for the entire structure. The fabricated three-axis MEMS capacitive accelerometer die measures $12\,\times \,7\,\times \,1$ mm3. The $x$ -axis and $y$ -axis accelerometers demonstrate measured noise floors and bias instabilities equal to or better than 5.5 $\mu \text{g}/\surd $ Hz and 2.2 $\mu \text{g}$ , respectively, while the $z$ -axis accelerometer demonstrates $12.6~\mu \text{g}/\surd $ Hz noise floor and $17.4~\mu \text{g}$ bias instability values using hybrid-connected fourth-order sigma–delta CMOS application specific integrated circuit (ASIC) chips. These low noise performances are achieved with a measurement range of over ±10 g for the $x$ -axis and $y$ -axis accelerometers and +12/−7.5 g for the $z$ -axis accelerometer, suggesting their potential use in navigation grade applications. [2014-0351]

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

Process Development for the Fabrication of a Three Axes Capacitive MEMS Accelerometer

This paper presents a new approach for the fabrication of a three-axis capacitive MEMS accelerometer that is capable of differentially sensing the acceleration in all three orthogonal axes. For the first time in literature, differential sensing for the out of plane direction is achieved by defining a movable sensing electrode on the structural layer of the SOI wafer that is sandwiched between two stationary electrodes defined on the glass substrate and the handle layer of the SOI wafer enabling the differential sensing. In this approach, individual lateral and vertical axis accelerometers are fabricated in the same die on an SOI wafer which is anodically bonded to a glass substrate.

Design and fabrication of a MEMS capacitive accelerometer with fully symmetrical double-sided H-shaped beam structure

This paper presents a MEMS capacitive accelerometer with fully symmetrical double-sided H-shaped beam structure. The fully symmetrical structure is fabricated from a single double-device-layer SOI wafer, which has identical buried oxide layer and device layer on both sides of a thick handle layer. A large proof mass with through wafer thickness (560μm) is fabricated in this process. Two layers of single crystal silicon H-shaped beams with highly controllable dimension suspend the proof mass from both sides. The resonance frequency of the accelerometer is measured in open loop system by a network analyzer. The quality factor and the resonant frequency are 106 and 2.24kHz, respectively. The accelerometer with open loop interface circuit is calibrated on B&K Vibration Transducer Calibration System (Type 3629). The sensitivity of the device is 0.24V/g, and the nonlinearity is 0.29% over the range of 0–1g.

Three-Dimensional Integration of Fully Depleted Silicon-on-Insulator Transistor Substrates for CMOS Image Sensors Using Au/SiO2 Hybrid Bonding and XeF2 Etching

Wafer bonding is a promising technology to enhance the performance and functionality of integrated circuits including memory devices, and large improvements have been made also in CMOS image sensors. In previous work, direct SiO2-SiO2 bonding and adhesive bonding techniques were employed to develop CMOS image sensors of a back-illumination type [1,2]. For cellular phone cameras, for instance, wafer bonding of an imaging pixel substrate and a logic circuit substrate was demonstrated to considerably reduce the chip size [3]. Cu-Cu bonding was reported to bond the III-V compound infrared detector array and the CMOS readout circuit, thereby reducing power consumption [4]. Wafer bonding is also expected to overcome the limitations of the conventional CMOS image sensors, such as dynamic range and signal processing capability [5,6].We have investigated an image sensor for future TV broadcast equipment, where pixel-parallel signal processing is needed. As shown in Fig. 1, three-dimensional (3D) device containing functional layers is made up of components such as photodiodes and signal processors through the pixel-wise vertical interconnections [7-9]. The signal from each photodiode is processed by the analog-to-digital converters within the pixel and read out in parallel. This new architecture allows a significantly large number of scanning lines than the conventional planar image sensors would do by the column-parallel signal processing architecture.To implement the structure of the image sensor, we developed a fabrication process for 3D integration of fully depleted silicon-on-insulator (FDSOI) transistor substrates by Au/SiO2 hybrid bonding and XeF2 etching [2,8]. Figure 2 shows a test chip that was experimentally constructed to demonstrate the effectiveness of this approach. The chip consists of a back-illuminated photodiode layer (upper substrate) and a signal processor layer (bottom substrate).Figure 3 illustrates the chip fabrication process. (a) FETs were first formed on FDSOI substrates. (b) Via holes were produced in the intermediate SiO2 layer by dry etching. (c) A Ti seed layer was deposited by sputtering and a Au film was formed by electroplating. (d) A Au/SiO2 hybrid surface was formed by chemical mechanical polishing (CMP), and the corresponding atomic force microscopy (AFM) image is shown in Fig. 4. (e) The hybrid surface was treated sequentially with Ar and O2 plasma, and the substrates were cooled to 15 °C to promote the absorption of water molecules on their surface. (f) The substrates were directly bonded using a force of 2000 N for 60 min at 200 °C and 1 Pa (Fig. 5(a)). (g) The Si handle layer of the upper substrate was removed to allow the light transmission to the photodiode. The handle layer was first thinned to 40 µm (Fig. 5(b)). (h) The remaining Si was removed by 75 cycles of XeF2 etching at 400 Pa for 30 s. Since the buried SiO2 acted as a natural etch stop, a completely smooth back surface could be obtained, as shown in Fig. 5(c). Figure 6 shows a cross-sectional scanning electron microscopy (SEM) image of the fabricated chip. Following the removal of the Si handle layer, the remaining thickness of the upper substrate was 6.5 µm. The alignment error was determined to be less than 3 µm and no interfacial voids were identified. From these results, it was concluded that a 3D test chip was successfully developed using the proposed method. This process is promising to stack more than 3 layers of substrate by repetition and to form additional backside electrodes [9].In conclusion, an experimental test chip was successfully fabricated using the Au/SiO2 hybrid bonding and the XeF2 etching to demonstrate the 3D integration of image sensor. The results clearly indicate the feasibility of fabrication method toward image sensors.

Fabrication of freestanding nanoscale gratings on silicon-on-insulator wafer

We report a bottom-up process for the fabrication of freestanding nanoscale gratings on silicon-on-insulator (SOI) wafer. Freestanding membrane devices suffer deflection due to the residual stress of the buried oxide layer of SOI wafer. The deflection will affect the device shape and result in the fracture problem for devices fabricated on thin silicon membrane. The bottom-up process is developed to overcome the fabrication issue for thin silicon membrane gratings. The silicon handle layer is removed through back wafer etching of silicon, where the buried oxide layer acts as an etch stop layer. The grating structures are then defined on thin silicon device layer by electron beam lithography and generated by fast atom beam etching. The grating structures are finally released in vapor HF to form the freestanding nanoscale gratings. The freestanding linear/circular gratings, 1,500-nm period grating with the grating width of 200- and 850-nm period grating with the grating width of 100 nm, are successfully achieved on 260-nm silicon device layer.

Silicon-based integrated millimeter-wave CPW-to-dielectric image-guide transition

In this article, a novel mm-wave dielectric image-guide DIG to CPW transition is proposed, fabricated, and successfully tested in the silicon technology. A DIG is implemented on high resistivity Silicon-On-Insulator SOI wafer. The image-guide height and handle layer thickness are 500 µm and 130 µm, respectively. An Aluminum coplanar waveguide is patterned over the DIG. The measured transmission characteristics of the transition are in acceptable agreement with the simulation results. A transition coupling loss of about 1 dB has been achieved at 60 GHz. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:490-497, 2014.

A dicing-free SOI process for MEMS devices based on the lag effect

This paper presents a dicing-free process for silicon-on-insulator (SOI) microelectromechanical systems (MEMS). In the process, the lag effect in deep reactive ion etching (DRIE) is used to form the breaking trenches. In the backside DRIE, the wide backside cavities are etched down to the buried oxide layer. The narrow breaking trenches, in contrast, are not etched to the buried oxide layer. Therefore, the narrow trench can be used to break the wafer after the entire process; in addition, the handle layer can still act as a bracing structure before ‘breaking’. Finally, the device layer is patterned, and a DRIE step is used to form the MEMS devices. In this way, the dicing step can be omitted to prevent further damages from high pressure water jets and silicon dust. Meanwhile, the process can also prevent notching simply because the insulating layer is removed before device etching. To demonstrate the feasibility of the proposed fabrication process, a micromachined gyroscope is designed and fabricated.

Calculating capacitance and analyzing nonlinearity of micro-accelerometers by Schwarz–Christoffel mapping

Designing micro-accelerometers requires the calculation of their capacitance. An analytical method based on the Schwarz---Christoffel mapping is proposed for the calculation of the capacitance of two types of micro-accelerometer, which enables the fringe effect to be taken into account. The two types of micro-accelerometer consist of four identical asymmetric comb-capacitors that produce a differential capacitance. For the micro-accelerometer without a handle layer under the comb-capacitor, only a single unit needs solving because the asymmetric comb-capacitor is composed of identical units. The analytical formula for the asymmetric comb-capacitor is verified by the three-dimensional finite element method. Through finite element method, the analytical formula is also extended to include asymmetric comb-capacitors of silicon-on-glass micro-accelerometers. A comparison between theoretical and experimental results from silicon-on-glass micro-accelerometers indicates the validity of the analytical formula. Based on the analytical formula, the nonlinearity of the micro-accelerometers is studied, which indicates that the high ratio between the wide and narrow gap distances can increase the linearity of micro-accelerometers.

Fabrication of a MEMS capacitive accelerometer with symmetrical double-sided serpentine beam-mass structure

This paper presents a symmetrical double-sided serpentine beam-mass structure design with a convenient and precise process of manufacturing MEMS accelerometers. The symmetrical double-sided serpentine beam-mass structure is fabricated from a single double-device-layer SOI wafer, which has identical buried oxides and device layers on both sides of a thick handle layer. The fabrication process produced proof mass with though wafer thickness (860 μm) to enable formation of a larger proof mass. Two layers of single crystal silicon serpentine beams with highly controllable dimension suspend the proof mass from both sides. A sandwich differential capacitive accelerometer based on symmetrical double-sided serpentine beams-mass structure is fabricated by three layer silicon/silicon wafer direct bonding. The resonance frequency of the accelerometer is measured in open loop system by a network analyzer. The quality factor and the resonant frequency are 14 and 724 Hz, respectively. The differential capacitance sensitivity of the fabricated accelerometer is 15 pF/g. The sensitivity of the device with close loop interface circuit is 2 V/g, and the nonlinearity is 0.6 % over the range of 0–1 g. The measured input referred noise floor of accelerometer with interface circuit is 2 μg/√Hz (0–250 Hz).

Out-of-plane nanomechanical tuning of double-coupled one-dimensional photonic crystal cavities

We demonstrate tuning of double-coupled one-dimensional photonic crystal cavities by their out-of-plane nanomechanical deformations. The coupled cavities are pulled by the vertical electrostatic force generated by the potential difference between the device layer and the handle layer in a silicon-on-insulator chip, and the induced deformations are analyzed by the finite element method. Applied with a voltage of 12 V, the cavities obtain a redshift of 0.0405 nm (twice the linewidth) for their second-order odd resonance mode and a blueshift of 0.0635 nm (three times the linewidth) for their second-order even resonance mode, which are mainly attributed to out-of-plane relative displacement. Out-of-plane tuning of coupled cavities does not need actuators and corresponding circuits; thus the device is succinct and compact. This working principle can be potentially applied in chip-level optoelectronic devices, such as sensors, switches, routers, and tunable filters.