Half-rate Decision Feedback Equalizer Research Articles

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

This work proposes a RX front-end structure, which is used for channel equalization of 25Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005mm2 designed in 65nm CMOS, the power consumption of which is 96mW under 1.2V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35dB at 12.5GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171mV and 0.61UI at the BER of 10-12, respectively.

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS

An ideal infinite impulse response (IIR) decision feedback equalizer (DFE) can have an effect on wireline received waveforms similar to a continuous-time equalizer, but without the associated amplification of noise and crosstalk. However, an IIR DFE's performance degrades significantly as the feedback loop delay increases. Fortunately, adding a single discrete-time tap can eliminate the degradation. The implementation of a half-rate DFE with two IIR taps and one discrete-time tap is presented here. The two IIR filters have different time constants to accommodate a variety of channel pulse responses having a long tail. The discrete-time tap cancels the first post-cursor inter-symbol interference (ISI) term and alleviates feedback loop timing issues. The DFE can receive data transmitted with a low swing of 150 mVpp-diff through 24 dB of channel loss at half the bitrate while consuming 4.1 mW at 10 Gb/s. Digital foreground calibration of clock phase shifters and offset cancellation is described. The receiver, including the DFE, clock buffers and clock phase adjustment, occupies an area of 8760 µm 2 in an ST 28 nm LP CMOS process.

A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes

This paper presents a 0.18 μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm2.

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28 Gb/s is 693 mW/lane.

A 1.0625 $\sim$ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

A robust transceiver designed for NRZ signaling beyond 10Gb/s over long-range physical media (including electrical backplanes, copper cables and optical modules) must contend with significant challenges from insertion loss, crosstalk, and reflection. For inter-symbol interference (ISI) cancellation, half-rate decision-feedback equalizer (DFE) with unrolled first tap [1–3] is widely used to avoid noise amplification and to relax timing for data sampling/feedback. However, tap-unrolling increases slicer count and entails half-rate multiplexers eating into timing margin. To remove reflection-induced ISI due to impedance discontinuities in the media, the DFE must cover tap positions higher than 30UI which is beyond tap range of the DFEs reported in previous work [1–4]. Fig. 1 shows an example of bumpy channel with reflection energy up to 40UI.

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization