H-bridge Multilevel Inverter Topology Research Articles

Design of Cascaded H-Bridge Multilevel Inverter Topology for Integrated Portable Power Pack Application

This paper presents the necessity of portable power supplies that can be carried and cater to all the users' demands. Since the energy storage of the portable power pack are coming from DC supply, it needs an inverter to convert the DC voltage into AC voltage. Most of the low-priced inverters in the market have a simple build and are inefficient, resulting in high THD that can cause the electrical appliance not to work properly. This project was focused on the most suitable inverter type where the cascaded H-bridge multilevel inverter with PWM switching technique was proposed. This type of inverter will produce a better THD and a higher output voltage level when the inverter level is increased. This theory was proved where 3-level, 5-level and 7-level of Cascaded H-Bridge Multilevel Inverter has a 52.05 %, 29.98 % and 21.94 % of voltage THD. These results prove that by increasing the output voltage level can reduce the voltage THD. For the hardware implementation, a 5-Level Cascaded H-Bridge Multilevel Inverter with PWM switching technique is chosen because it has a lower voltage THD compared to 3-Level Cascaded H-Bridge Multilevel Inverter and at the same time use less of semiconductor devices compared to 7-Level Cascaded H-Bridge Multilevel Inverter and has fewer semiconductor losses compared to the inverter with SPWM switching technique. The voltage THD of circuit models hardware when reaches 24 V_pk is 28.3 % which is slightly better to simulation result, 29.98 %. This inverter was then connected with a step-up transformer with a ratio of 1:10 to reach standard electrical voltage supply in Malaysia of 230 V_rms with a voltage THD of 28.4 % without load and 30 % with load. This proves that the circuit model can work properly as the 5-Level Cascaded H-Bridge Inverter simulation and hardware results show a good agreement.

Evolutionary Metaheuristic Methods Applied to Minimize the THD in Inverters: A Systematic Review

In recent research works, metaheuristic methods have been widely used to minimize THD in inverters, these methods provide better computation time and effective results compared to classical methods. This paper presents a systematic analysis with a comprehensive coverage of metaheuristic methods applied to multilevel inverters. The search focused on the characteristics of the inverters used in the articles (topologies, levels, loads and evolutionary method). The aim is to show which are the characteristics of the most used case studies for the application of evolutionary metaheuristic methods. The IEEEXplorer, ScienceDirect, IET Digital Library, Springer and WorldWideScience databases have been used for the review since 2010. The results of the review show that many researchers use evolutionary algorithms, with Cascaded H-bridge Multilevel Inverter topology, RL loading and 7 levels. This highlights which features of the case studies are the most used and analysed to explore the advantages of using evolutionary metaheuristic methods.

PSO Based Selective Harmonic Elimination PWM for Cascaded H-Bridge Multilevel Inverter

A Single phase Cascaded H-bridge multilevel inverter topology fed by Photovoltaic source for the reduction of harmonics is proposed in this paper. Selective Harmonic Elimination technique is employed for elimination of 5th, 7th, 11th and 13th lower order harmonics and the particle swarm optimization algorithm is employed for estimating the switching angles. As a novelty, in order to maintain the power balance among the various sources, a cyclic selection procedure is adopted that over a period of operation also the sources equally contribute for the output power. MATLAB software is used for optimization and the results show the effectiveness of the proposed algorithm. The performance of the Particle Swarm Optimization Algorithm has been compared against the performance of the Genetic Algorithm.

Three-Phase Trinary Asymmetric Multilevel Inverter With Single DC Source and Open-Loop Control

A three-phase trinary-asymmetric cascaded H-bridge multilevel inverter topology with single dc source per phase is presented in this paper. Only one of the H-bridges (called Main bridge) is fed from a dc source and all others (called auxiliary bridges) derive their dc links from floating capacitors. Existing literature mostly depend on closed loop control schemes to stabilize the dc link voltage. This paper proposes a new open loop control strategy for balancing of voltage across floating capacitors naturally. DC bus voltages of the auxiliary bridges are converged to maintain a trinary asymmetric ratio with the main-bridge by selecting the right set of space-vectors. Modulation of the inverter is carried out by exploring the space-vector redundancies that will help in achieving natural balancing of capacitor voltages. Selection of number bridges to be cascaded depends on criteria such as the allowable time of convergence, number of switching devices, acceptable power quality indices etc. Considering such constraints, a system with three cascaded cells per phase is found to exhibit satisfactory performances. Hence in this paper, simulation results obtained in MATLAB/ Simulink based model corresponding to such a system are presented. Experimental results observed on a laboratory prototype matched well with the simulation.

Grid-connected photovoltaic system employing a single-phase T-type cascaded H-bridge inverter

This paper presents the control and application of a single-phase T-type nine-level cascaded H-Bridge (TCHB) multilevel inverter (MLI) topology. This paper focuses on the effectiveness of the TCHB and its control by presenting the inverter operation based on a PI current controller along with a Maximum Power Point Tracking (MPPT) scheme to realize a grid-tied photovoltaic (PV) system and a novel PWM method offering self-balancing at the DC-link capacitors. In order to attain gating signals for power transistors (IGBTs), the TCHB employs a PWM with one triangular carrier signal and eight reference signals. In addition, a mathematical modelling of the PWM method, along with a theoretical explanation of the self-balancing process has also been provided. To prove the effectiveness of the proposed TCHB topological design, it has been comparatively analysed against other fundamental MLI and symmetric CHB topologies. In addition, to corroborate the working of the control and the PV system application, employing TCHB inverter offering nine output voltage levels (±2Vdc, ±2¾Vdc, ±Vdc, ±½Vdc, 0), simulation and hardware results have been presented.

THD analysis for symmetrical five level and seven level cascaded multilevel inverter

Total Harmonic Distortion (THD) is one of the problems in the multilevel inverter. This paper discussed a brief review of THD in different cascaded H-bridge multilevel inverter topologies of five levels and seven levels at the output waveforms. The five levels inverter contains eight switches while seven levels inverter used twelve switches. Each single H-bridge inverter circuit is fed by equally independent DC source for both inverters. The inverter uses MOSFET as the switching point and acts as the controller for a fundamental switching operation. The switching value has been set at the gating block to control the operation of the MOSFET switching. Several waveforms and simulation findings are provided to validate the quality of the proposed topology.

Medium Voltage Impedance-Admittance Measurement System Based on the Cascaded H-Bridge Multilevel Converter

Recent trends in power system design such as an increasing share of renewable energy sources and smart grids are creating different subsystem interactions that require proper investigation, understanding, describing and estimating global system stability through impedance-admittance measurement and identification. This paper proposes and presents the cascaded H-bridge multilevel inverter topology for perturbation injection converter and impedance-admittance measurement. The methodology of impedance-admittance measurement is explained together with different measurements requirements. Performance and suitability of this topology for impedance-admittance measurement is evaluated through simulations. Preliminary design principles are given for the converter. System level feasibility of the solution is proposed as a main result of the work.

An Improved Model Predictive Controller for 27-Level Asymmetric Cascaded Inverter Applicable in High-Power PV Grid-Connected Systems

The asymmetric cascaded H-bridge multilevel inverter (MLI) topology is more suitable for high-power/high-voltage applications compared with other topologies if the highest voltage H-bridge (the main cell) is modulated with the grid frequency (50/60 Hz). With specific modulation indexes, the power that passes through the main cell is more than 80% of the total power. This improves the efficiency and limits leakage current to the grid. However, achieving such a task is challenging using linear controllers and it was not proposed before in the literature using nonlinear controllers. This article presents a novel finite control set model predictive control (FCS-MPC) algorithm suitable for high-voltage/high-power single-stage central inverter connecting photovoltaic (PV) system to the grid. In addition to tracking the reference, multiple constraints are proposed; the first constraint is to modulate the main cell with the grid frequency, and the second constraint is to achieve nonregenerative operation in the lower voltage (the auxiliary) H-bridge cells to ensure the unidirectional power flow for the prerectifier. It should be noted that such constraints using weight factors added to the cost function in conventional FCS-MPC are not applicable to the implementation because the application requires separate independent control signals to individual H-bridge cells. Therefore, the proposed FCS-MPC controller implements the constraints using individual algorithms added to the respective H-bridge cell control signals. The proposed algorithm results in better mymargin THDs in the output current waveform compared with previous schemes. Furthermore, a duty-cycle optimization algorithm is implemented in addition to the conventional algorithms to achieve reduced errors at a relatively lower sampling frequency. The controller is verified and implemented using 2kW hardware prototype for grid-connected operation.

Cascaded H-Bridge MLI and Three-Phase Cascaded VSI Topologies for Grid-Connected PV Systems with Distributed MPPT

Cascaded multilevel inverter topologies have received a great deal of attention for grid-connected PV systems. In this paper, three-cascaded multilevel inverter configurations are proposed for grid-connected PV applications. These are the three-phase cascaded H-bridge multilevel inverter topology, three-phase cascaded voltage-source inverter topology using inductors, and three-phase cascaded voltage-source inverter topology using coupled transformers. Distributed maximum power point tracking (MPPT) of PV modules using perturbation and observation algorithm is used for all presented topologies. In all presented configurations, each PV module is connected to one DC-DC isolated Ćuk converter for best MPPT achievement. Simulation is achieved by using the SIMULINK environment. The simulation results show that the three proposed topologies function well in improving the grid’s power quality. The grid currents are kept in phase with the grid voltage to ensure unity power factor, and the THD of the grid currents are within the acceptable range. The proposed topologies are experimentally implemented in the lab, and the switching pulses are generated with the help of the MicroLabBox data acquisition system. Comparing the three topologies according to the number of switches, voltage, and current stresses on switches and THD of the generated voltages and grid currents and according to the efficiency has been achieved in this paper, both experimentally and by simulation. The simulation and experimental results and comparisons are presented to verify the proposed topologies’ effectiveness and reliability.

Modeling and Simulation of Nine-Level Cascaded H-Bridge Multilevel Inverter

This paper analyzed a single phase nine level cascaded h-bridge multilevel inverter (CHMLI) topology in which requires lesser number of components and easier to control if compared to other methods. The inverter of different voltage levels (up to 9-Levels) are designed and simulated using MATLAB Simulink. A Level Shifted Multi-Carrier PWM control scheme is used to control the operation of the power switches for CHMLI topology. The results are compared in terms of THD. The value of THD is found to be reduced as the number of voltage level of CHMLI is increased.

A Single Phase 7-Level Cascade Inverter Topology with Reduced Number of Switches on Resistive Load by Using PWM

This paper discussing design principles of inverter structure with reduced number of semiconductor devices of seven levels symmetric H-bridge multilevel inverter (MLI) topology. The aim of this paper is to design an inverter circuit with reduction of semiconductor losses, converter size and development cost. The H-bridge and auxiliary structures were considered in order to achieve seven levels output voltage. The performance of design circuit is compared with conventional seven levels structure in terms of voltage output. The circuit development consists of seven switches and three diode. A basic modulation technique is used to confirm the designed circuit. The results show that the designed circuit is able to convert seven level output voltage with low total harmonics distortion (THD) in voltage fundamental output. According to the results, fundamental output voltage is increased up to 8.314%, and the THD is decreased up to 0.81% compared to the conventional seven level inverter.

Phase-Shifted Carrier-Based Synchronized Sinusoidal PWM Techniques for a Cascaded H-Bridge Multilevel Inverter

This paper analyzes synchronization strategy for cascaded H-bridge multilevel inverter (CHBMLI) topologies with a carrier-based sinusoidal phase-shifted pulse width modulation (PSPWM) technique. In the PSPWM technique, a separate carrier is used for each H-bridge (HB). The carriers are generally phase shifted from each other by π/x rad (x = No. of HBs) for unipolar PWM. With the carrier frequency being an integer (odd/even) multiple of the fundamental frequency, it is observed that the positions of zero crossings of the carriers with respect to the zero crossings of voltage references play an important role for maintaining quarter-wave symmetry among multilevel inverter pole voltage waveforms. This paper analytically shows the conditions for half-wave symmetry and quarter-wave symmetry and experimentally verifies those conditions for the PSPWM technique with a five-level CHBMLI laboratory prototype.

Design and Simulation of Single-Phase Five-Level Symmetrical Cascaded H-Bridge Multilevel Inverter with Reduces Number of Switches

Multilevel inverter is an effective and practical solution for increasing power demand and reducing harmonics of ac waveforms. Such inverters synthesize a desired output voltage from several levels of dc voltages as inputs. This paper analyzes the performance of five level cascaded H-bridge multilevel inverter with reduce number of power switches. Further by reducing switches and increasing level will reduce filter cost & harmonic content. 5- Level cascaded H-bridge asymmetrical multilevel inverter topology requires 8 switches but in this new multilevel inverter it requires 6 switches in which same multilevel is obtained. Invariably switching losses and cost also reduced. In this paper only multilevel inverter circuitry will be studied. The performance has been analyzed by the MATLAB/Simulink.

A Novel Symmetrical Cascade H-Bridge Multi-Level Inverter Topology with Reduced Switching Devices

A Novel Symmetrical Cascade H-Bridge Multi-Level Inverter Topology with Reduced Switching Devices

Neutral Point Clamped and Cascaded H-Bridge Multilevel Inverter Topologies – A Comparison

Objectives: This work emphasizes on the analysis of two five levels inverter topologies - neutral point clamped topology and Cascaded H-Bridge inverter topology. Methods/Analysis: The neutral point clamped topology requires only one DC source, eight switches and four clamping diodes with two voltage balancing capacitors. The cascaded topology carries two voltage sources and eight switching devices. Phase disposition pulse width modulation technique generates gating pulses for both the multilevel inverter topologies. All the simulations are done in MATLAB-Simulink simulation environment. Findings: The output waveforms, switching stress and harmonic spectrum of the output waveforms of both the inverter topologies are obtained using phase disposition pulse width modulation technique for a modulation index of unity. Moreover, the work aims to perform a comparison of both the inverter topologies with respect to total harmonic distortion, switch stress and complexity of the topology. It is found that though a cascaded inverter needs less overall components when compared to neutral point clamped inverter, yet both the inverter topologies carries the same stress across their switches and produce an almost the same harmonic distortion on their output waveforms. Applications/Improvement: Conventional voltage source inverters are gradually being replaced by multilevel inverters in various applications like photovoltaic systems, reactive power compensators, FACTS devices, adjustable speed drives etc. The stress across each of the switches gets decreased in both the multilevel inverter topologies compared to conventional inverters. Further, neutral point clamped inverters carry the advantage of requiring only one DC source for its operation.

Analysis of various control schemes for minimal Total Harmonic Distortion in cascaded H-bridge multilevel inverter

Multilevel inverters are becoming more popular in the power conversion systems for high power and power quality demanding applications. The MATLAB based simulation on SIMULINK platform is presented for the Single Phase five level cascaded H-bridge Multilevel Inverter (CHB-MLI) topology with less number of switches and with different control schemes and Sinusoidal Pulse Width Modulation (SPWM) schemes. A detailed comparison of various control schemes is presented in this paper with reference to Total Harmonic Distortion (THD) in the output voltage and utilization factor of the power devices. It is observed that among all the control schemes, the THD is minimum in the Sinusoidal Pulse Width Modulation-Phase Disposition (SPWM-PD) scheme with variable carrier wave magnitude.

Synchronverter Control for Parallel Operation of Cascaded H-Bridge Inverter

<p>A 21-levels cascaded H-bridge multilevel inverter topology based on three-phase voltage source inverter has been proposed as a superior replacement for conventional two-level in high voltage applications. In this work we have presented the usage of the new technique called virtual synchronous generator based synchronverter model to operate the multilevel inverter as synchronous generator, and to share active and reactive power automatically in case of parallel operated inverters of the same type. Carrier-based PWM is used to control each phase leg of the cascaded H-bridge multilevel inverter. This carrier-based PWM scheme is derived from the carrier phase disposition pulse width modulation strategy. By aid of MATLAB/Simulink package a simulation experiment is established to verify the performance of the proposed technique.</p><p> </p>

Capacitor Pattern H-Bridge Multilevel Inverter (CPHMLI) Using Phase Diposition Pulse Width Modulation for Grid Applications

This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.

Power Conditioning for a Small-Scale PV System with Charge-Balancing Integrated Micro-Inverter

The photovoltaic (PV) power conditioning system for small-scale applications has gained significant interest in the past few decades. However, the standalone mode of operation has been rarely approached. This paper presents a two-stage multi-level micro-inverter topology that considers the different operation modes. A multi-output flyback converter provides both the DC-Link voltage balancing for the multi-level inverter side and maximum power point tracking control in grid connection mode in the PV stage. A modified H-bridge multi-level inverter topology is included for the AC output stage. The multi-level inverter lowers the total harmonic distortion and overall ratings of the power semiconductor switches. The proposed micro-inverter topology can help to decrease the size and cost of the PV system. Transient analysis and controller design of this micro-inverter have been proposed for stand-alone and grid-connected modes. Finally, the system performance was verified using a 120 W hardware prototype.

Three-Phase Asymmetric Multilevel Inverter Topologies with Better Charge Balancing

Cascaded H-bridge multilevel inverter is among the most preferred topology in solar systems. While traditional asymmetric cascaded H-bridge multilevel inverter is easy to achieve higher number of output voltage levels compared to traditional symmetric cascaded H-bridge multilevel inverter, charge balancing between the voltage sources remains a challenge for asymmetric cascaded H-bridge multilevel inverter. This drawback results in unsteady DC voltage levels due to unbalanced power drawn from each voltage sources. Besides that, in battery powered applications, unbalanced power drawn results in unequal discharged in the batteries. In this paper, two three-phase asymmetric cascaded H-bridge multilevel inverter topologies are proposed which offer easier in terms of modularity while maintaining the ease in charge balancing control. The performance of these two proposed topologies with charge balance control has been evaluated using PSIM software.