GSM Receiver Research Articles

Smart Safety with Password Based GSM Module Controlling Circuit Breaker

Abstract: This paper focus on Smart safety with password based GSM module controlling circuit breaker. In our daily life, Safety is the major concern for all activities. Accidental death of a lineman is often read and proven in current scenario. In view, safety measures to protect operators are considered to be very necessary in current working. Using passwords for security, Electrical lineman security systems are used to control circuit breakers. Serious electrical accidents occurs becoming increasingly, when repairing power lines. It is happen due to lack of communication and coordination between maintenance and substation personnel. In the proposed system, the on and off line turning operation with the lineman to ensure the safety of linemen. For that, a secure password is required to operate the breaker operation and maintenance point of view. First request is registered and password is sent to the line operator's mobile phone and GSM module by AVR microcontroller. Entered password and password received by the GSM receiver are compare. If password is match, the operation of circuit breaker will be smoothly operate. The operator gave three chances for incorrect password otherwise message will appear on the LCD display for security purposed. It also sent the message control room regarding unauthorized access to the system.

Development and evaluation of automation system for irrigation scheduling in broccoli (Brassica oleracea)

The present study was attempted to develop an automated irrigation system for real-time irrigation management using soil moisture sensor, decision support system, level sensor, level controller, GSM receiver, transmitter, solenoid valve, water meter and pump. The performance of developed automated irrigation system was evaluated under different methods of irrigation in broccoli crop. The field experiment in Broccoli crop was conducted (2013-14 and 2014-15 ) in split plot designwith three irrigation methods, i.e. check-basin, furrow and drip irrigation as main plot treatments, and irrigation control methods, i.e. automated and manually-controlled assub-plot treatments. Water saving, water productivity and cost economics of developed system were calculated and compared under different studied irrigation methods. It was found in the present study that the sensor based automated drip irrigation system resulted in highest irrigation water productivity (9.7 kg/m3) and crop water productivity (10.6 kg/m3) as compared to all other treatments. Similarly, the highest benefit-cost ratio (3.24) and water saving was obtained under the sensor based automated drip irrigation system. Therefore, the developed indigenous sensor based automated drip irrigation system can be used for efficient irrigation management in the broccoli crop.

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

Information technology for remote forced vehi-cle speed limits to improve road safety

Problems. Overcoming the consequences of traffic accidents places a heavy burden on the country's health and social services. The International Transport Forum has developed the report “Striving for Zero: High Tasks and a Systematic Approach to Traffic Safety”. Forum experts consider non-compliance with the high-speed regime on roads to be a key problem in the growth of road accidents, and the use of information technologies is one of the ways to reduce accidents. Goal. Based on the analysis, we formulated the goal of the study, which consists in creating a method and device for remote forced speed limits (RFSL) of vehicles on roads in the city and outside it in accordance with the speed limit adopted at this place. The task of this article is to formulate a concept for improving road safety in Ukraine in terms of bringing vehicle speeds to the maximum allowable values for these roads (the concept is outlined and justified), as well as developing a functional diagram of a device for remote forced vehicle speed limitation. Methodology . The analytical method is research of existing systems that can remote forced speed to limit. The method of synthesis is creation the structural scheme of a new system, based on the advantages and disadvantages of analyzed systems. Results . A method of improving road safety by remote forced speed limits of cars on roads within the city and outside them in accordance with the accepted speed limit in this place is the constant transmission over mobile networks or any other communication signal carrying information about the restrictions speed in a specific place on a specific highway. This signal after reception is processed in the microprocessor control system of fuel supply to the car engine according to a certain algorithm for the purpose of maintenance of a car speed, which does not exceed the value of restriction. Moreover, the driver of the vehicle could not, even if he wanted to, compromise such a restriction. Originality . The method of remote forced speed limitation of the car works as follows. The GSM receiver (possibly another radio receiver) constantly receives a signal that carries the value of the speed allowed on this road. In a microprocessor control unit (MCU), this value is compared to a signal from a digital speedometer or speed sensor, which is the current value of the vehicle speed. The inconsistency of these two signals or exceeding the speed of the car over the allowable speed on this road is the basis for recalculation (reduction) according to the programmed algorithm by the MCU unit of the amount of fuel required to feed the injector, as well as to reduce the duration of injectors. Reducing the fuel supply to the engine cylinders lowers the speed of the car to the acceptable values. Practical value . Functional schemes of devices for realization of the offered way on the basic types of control systems of the engine in modern cars are developed. As an example, a generalized universal functional diagram of a device for remote forced limitation of vehicle speed is given. Key words . traffic safety, speeding, remote forced vehicle speed limit, microprocessor, controller.

A Reliable Gait Analysis Using Fuzzy Logic

In this paper, an artificial intelligence technique which is fuzzy logic is used as an online prediction of a patient (especially Alzheimer patient) motion status. It depends on the input variables: GPS, GPRS, accelerometer, gyroscope, temperature, heartbeat rate, and the motion status (standing, walking, and running) as an output variable. Fuzzy logic can detect the motion status based on 385 rules for all inputs and output variables. A low-cost smart shoe with embedded positioning tracking is implemented based on sensors and microcontrollers to help Alzheimer patients. The first phase of the experimental work is based on GPS, GPRS, GSM, accelerometer, heartbeat rate sensor, temperature sensor, and a microcontroller, mounted on the shoe side to navigate according to the pedestrian or patient movement. All sensors data are collected by the microcontroller and are transmitted to the GSM receiver in SMS message. The GSM module is connected to the PC via a USB serial port. Transmitting data is periodically sent upon a specific time. The detected data is stored in the database as a function of time. The data includes the position of the patient (latitude and longitude) located on the Google map software, health status (heartbeat rate), gyroscope and accelerometer (x, y, z) of movement as a function of time.

Password Based Distribution Panel and Circuit Breaker Operation for the Safety of Lineman during Maintenance Work

Security is the prime concern in our day to day life while performing any activity. In the current scenario, accidental death of lineman is often read and evidenced. In this direction, a safety measure to safe guard the operator is found very necessary looking into the present working style. The electric lineman safety system is designed to control the control panel doors and circuit breaker by using a password for the safety. Critical electrical accidents to lineman are on the rise during electric line repair may be due to lack of communication and co-ordination between the maintenance staff and electric substation staff. The proposed system provides a solution that ensures safety of lineman. The control to turn ON or OFF the line is maintained by the lineman. The system has an arrangement such that a password is required to operate the doors of the control panel and circuit breaker (ON/OFF). A secured password is requested and received from the control room by the lineman for the point of repair or service. This request is registered and a password is sent to the lineman’s mobile and control panel GSM module for the further work. The password is entered through the matrix keypad which is interfaced to the Arduino Uno microcontroller. The entered password is compared with the password received by the control panel GSM receiver. If the entered password is correct then the circuit breaker ON/OFF and door OPEN/CLOSE feature is enabled for the lineman to take up repair. Any intruder tries to operate the mechanism with the wrong password by three times it will display a message in the LCD display and a message is sent to the control room regarding unauthorized accessing of the system for the safety reasons.

Adaptive IF selection and IQ mismatch compensation in a low-IF GSM receiver

This paper presents an algorithm that can adaptively select the intermediate frequency (IF) and compensate the IQ mismatch according to the power ratio of the adjacent channel interference to the desired signal in a low-IF GSM receiver. The IF can be adaptively selected between 100 and 130 kHz. Test result shows an improvement of phase error from 6.78° to 3.23°. Also a least mean squares (LMS) based IQ mismatch compensation algorithm is applied to improve image rejection ratio (IRR) for the desired signal along with strong adjacent channel interference. The IRR is improved from 29.1 to 44.3 dB in measurement. The design is verified in a low-IF GSM receiver fabricated in SMIC 0.13 μm RF CMOS process with a working voltage of 1.2 V.

Enabling collocated coexistence in IEEE 802.16 networks via perceived concurrency

Multiple wireless interfaces (GSM, Wi-Fi, Bluetooth, FM, and GPS receiver, etc.) are being integrated into mobile devices. WiMAX, an IEEE802.16-based wireless access technology recently included in the IMT-2000 set of standards by ITU-R, will soon be added. Obstacles remain to operating these collocated radios concurrently, including interference and hardware conflicts due to congested spectrum allocation and component sharing with radio integration. In this article we provide a tutorial overview of today's solutions to enable concurrent operation of multiple collocated radios in IEEE 802.16- based wireless networks with a focus on perceived concurrency: a MAC coordination approach. We then present three general design principles - predictability, compressibility, and flexible scheduling - with examples of standard features. It is anticipated that the next-generation IEEE 802.16 standards will be enhanced with new features such as explicit service setup, asynchronous operation, and collocated coexistence-aware scheduling.

Predictive test strategy for CMOS RF mixers

In this paper, we present two built-in self-test strategies for the down-converter stage in a GSM receiver. These strategies are based on the prediction of its performance parameters from measurements in test mode. By reusing some receiver blocks as part of the test set-up, the circuitry overhead is kept small. The first strategy uses the local oscillator (LO) signal as the only test stimuli. The second strategy uses additional test circuitry, a generator, and an auxiliary mixer. Prediction accuracies are similar in both strategies, but the test observables in the second one are easier to be obtained.

H∞ Filtering Approach for GSM Navigation Systems

The GSM navigation system designs using H∞ filtering approach is conducted and the resulting performance is assessed. The H∞ filtering problem is shown to have many solutions for each proper value of the prescribed design parameter γ, which is different from the Kalman filter with only one solution. The Kalman filter, which employed in the GSM receiver as the navigational state estimator, provides optimal solution if the noise statistics for both the measurement and the system process are completely known. Practically, the noises are varying with time, which results in filtering performance degradation. In design, H∞ filter can be employed to ensure that the energy gain from the disturbances to the estimation error will not exceed an upper bound.

An IIP2 Calibration Technique for Zero-IF Multi Band down Converter Mixer

Meeting the tough linearity and noise required by GSM and UMTS receivers in CMOS technology is challenging. A new IIP2 calibration technique based on canceling the second order nonlinearities of mixer, generated in the input RF transistors, is introduced. By using this technique about 22 dB mixer IIP2 improvement is achieved. The proposed calibration circuit can be used in multi-standard mixer because of high bandwidth of the calibration circuitry. Moreover it can work with voltage supplies as low as 1 V. Using this technique a multi-standard mixer supporting PCS, UMTS and IEEE802.11b-g is developed. The design is done in CMOS 65 nm technology with 1.2 V supply while it consumes about 7 mA current.

A Module for BiST of CMOS RF Receivers

A module to perform a built-in self-test in CMOS RF receivers is presented. The module is associated with a test strategy consisting of measuring the main performance parameters of the single building blocks individually. Circuitry overhead, however, is kept low by using some blocks as part of the test set-up and reusing them. The test overhead has also been reduced by replacing direct determination of performance parameters with their estimation. The test methodology has been applied to a mixer in the first down conversion stage of a GSM receiver, estimating its conversion gain, 1dB compression and third-order interception points. Using the output of the IF amplifier as the only testing point, the rms errors in the estimation of the above mentioned parameters are 1.5, 3.0 and 2.7%, respectively.

A New Inductor-Less IP2 Enhancement Technique for CMOS Multi-Standard Mixer

The linearity and noise required by GSM and UMTS receivers make the design of a CMOS mixer for these applications so challenging. A new technique for IP2 improvement in Zero-IF active mixers is presented in this paper. This inductor-less technique is based on canceling the parasitic capacitor of common source node of the switching transistors and synthesizing resistive impedance. Using this technique, a reconfigurable down converter mixer works from 900MHz to 2.4 GHz is designed supporting GSM, DCS, PCS, UMTS and IEEE802.11 b-g standards. The mixer IIP2 is higher than 71 dBm in GSM and UMTS bands. The mixer conversion gain is higher that 12 dB in all frequency bands. The design is done in 65 nm CMOS technology and consumes 10mA from a 1.2V supply. The design meets the performance required for all mentioned standards, while its area and power is comparable with high performance single band mixers.

A new technique for high IIP2 reconfigurable CMOS mixer in multi-standard receivers

A new technique for addressing the challenging dynamic range required by CMOS multi-standard Zero-IF GSM and UMTS receivers is presented in this paper. This is achieved by LC tuning of the parasitic capacitors of mixer switching transistors in different frequency bands with an easily reconfigured new integrated variable inductor. Using this technique, a high IIP2 low noise mixer supporting DCS, PCS, UMTS and IEEE802.11 b-g standards is designed. The mixer achieves IIP2 higher than 70dBm while the input refereed noise performance is 5 and 3.5nv/sqrt(Hz) in DCS/PCS and UMTS respectively. The design is done in 65nm CMOS technology.

Dynamic Power Optimization of Active Filters With Application to Zero-IF Receivers

This paper describes the use of dynamic impedance scaling and dynamic biasing to dynamically optimize the power dissipation of filters depending on the inband signal level. Transients due to the dynamical changes inside the filter are prevented thanks to the implementation of appropriate switching algorithms. To illustrate the concept, a fifth-order Chebychev low-pass active-RC filter with 100-kHz cutoff frequency, designed for partial channel selection in a zero-IF GSM receiver, is presented. The filter is fabricated in a standard 0.18-/spl mu/m CMOS process and uses a 1.2-V power supply. It consumes 2.22-mA supply current during the presence of the minimum receivable signal. The power dissipation decreases by a factor of 2 as the desired signal strength increases by 3 dB, until it reaches its minimum possible value of 0.46 mW. There are a total of five power settings in the filter.

A 1.5-V Multi-Mode Quad-Band RF Receiver for GSM/EDGE/CDMA2K in 90-nm Digital CMOS Process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.

Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers

RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digitally intensive domain for a wireless RF transceiver, so that it enjoys benefits of digital and switched-capacitor approaches. Direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio. We further present details of the RF receiver front end for a GSM radio realized in a 90-nm digital CMOS technology. The circuit consisting of low-noise amplifier, transconductance amplifier, and switching mixer offers 32.5 dB dynamic range with digitally configurable voltage gain of 40 dB down to 7.5dB. A series of decimation and discrete-time filtering follows the mixer and performs a highly linear second-order lowpass filtering to reject close-in interferers. The front-end gains can be configured with an automatic gain control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations. Even under the digital switching activity, noise figure at the 40 dB maximum gain is 1.8 dB and +50 dBm IIP2 at the 34 dB gain. The variation of the input matching versus multiple gains is less than 1 dB. The circuit in total occupies 3.1 mm2 . The LNA, TA, and mixer consume less than 15.3 mA at a supply voltage of 1.4 V.

I/Q Mismatch Compensation Using Adaptive Decorrelation in a Low-IF Receiver in 90-nm CMOS Process

We present a single multiplier based adaptive I/Q mismatch compensation circuit for narrowband quadrature receivers. Adaptive decorrelation between I and Q channel data is used for correcting gain and phase mismatches. Adaptation step size is computed from L/sub 1/-norm inverse power measurement and a gear-shifting mechanism is used that allows fast initial convergence and slow adaptation on actual burst data. Image rejection ratio in excess of 50 dB is reported for GSM receiver after compensation allowing the receiver to use IF frequencies higher than half of the channel bandwidth. The presented mismatch compensation circuit is implemented as part of a single-chip GSM wireless transceiver fabricated in a 90-nm digital CMOS process. The presented techniques are, however, equally applicable to other narrowband packet-based applications.

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass ΣΔ modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (Gm-C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the ΣΔ modulator. Implemented in a MOSIS HP 0.5-μm CMOS technology, the chip area is 857 μm × 420 μm, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.