Growth Of Ge Layers Research Articles

Metal-induced lateral crystallization of germanium thin films

Recent advances in polycrystalline Ge layers formed through solid-phase crystallization have demonstrated carrier mobilities superior to those of single-crystal Si. In this study, we thoroughly examined the phenomenon of metal-induced lateral crystallization in Ge, a topic that had garnered significant attention in Si research and had shown promise in improving the performance of thin-film transistors. Of the 24 metals tested (Au, In, Bi, Pb, Ga, Ag, Al, Sn, Zn, Sb, Fe, Nb, Mg, Mn, Co, Cr, Mo, Zr, Cu, Ni, Pd, Ta, Ti, and W), 20 were found to promote the low-temperature (<400 °C) lateral growth of Ge layers on glass. Based on the reaction type (eutectic or compound), reaction temperatures, diffusion coefficients, and domain matching analyzed using a materials informatics method, the growth morphology was categorized into three types: alloy, dendrite, and uniform. The knowledge of metal-induced growth obtained in this study has broad implications for a variety of materials and holds potential for developing the next generation thin-film devices with common and inexpensive substrates.

High Quality Ge Growth on Si (111) and Si (110) by Using Reduced Pressure Chemical Vapor Deposition

Heteroepitaxial growth of Ge on Si has great interest for various optoelectronic applications such as Ge photodiodes(1). However 4.2% of lattice mismatch causes dislocation formation and island growth. High quality Ge(001) growth techniques are reported in ref.(2-4). Moreover, Ge(111) surface is also interesting because of higher carrier mobility(5). Furthermore, Ge(110) is preferred orientation of virtual substrates for epitaxial graphene growth(6). In the case of the Ge deposition on Si(111) and Si(110) substrates, it seems that the process conditions used for Ge growth on Si(001) are not suitable to realize high crystallinity and smooth surface (7). In this paper, we present a method of high quality and smooth Ge layer growth on Si(111) and Si(110), which is the same level as the Ge growth on Si(001).Epitaxial growth of Ge on Si(111) and Si(110) is carried out using a reduced pressure chemical vapor deposition system. After HF last clean, a wafer is baked at 1000°C and cooled down to 600°C in H2 and further to 300-550°C in N2 to form a hydrogen-free Si surface. Then a 100 nm thick Ge layer is deposited as a seed layer using GeH4 with N2 carrier gas. Afterward the wafer is heated up to 450-650°C in H2 and the main part of Ge is deposited using a H2-GeH4 gas mixture. For threading dislocation density (TDD) reduction, annealing at 800°C in H2 is performed for several times (cyclic annealing) by interrupting the Ge growth. Atomic-force microscopy (AFM) is used for surface roughness analysis. Scanning transmission electron microscopy (STEM) and X-ray diffraction (XRD) are used for structural characterization of the Ge layer. Secco defect etching combined with angle view scanning electron microscopy (SEM) or optical microscope is used for TDD evaluation.Figure 1(a,b) summarize the root mean square (RMS) roughness of Ge(111) and Ge(110) seed layers grown at 300-550°C before and after postannealing at 600-800°C. If the growth temperature is lower than 350°C for Ge(111) and 400°C for Ge(110), a significant increase of the surface roughness is observed after postannealing at 700°C and 800°C, respectively. For both crystal orientations, the lowest RMS roughness is observed by depositing at 450°C for as deposited and postannealed samples. The maintained RMS roughness even after postannealing at 800oC may be indicating good crystal quality even at as deposited condition.To confirm the influence of the growth temperature on the crystallinity, cross section TEM images of the Ge(111) and the Ge(110) seed layers deposited at 300°C and 450°C are shown in Fig. 2(a-d). In the case of Ge growth at 300°C (Fig. 2(a,b)), a very high density of stacking faults (SF) and high surface roughness are observed for both crystal orientations. In contrast, by depositing at 450°C (Fig. 2(c,d)), lower SF density in the Ge layer is observed compared to that at 300°C. By postannealing, an improvement of crystallinity is observed for the Ge seed layers deposited at 450°C. However, in the case of 300°C, the crystallinity cannot be improved by the postannealing, because a too high density of dislocations and SF may cause irregular Ge atom migration. As the result, surface roughening occurs.Figure 3(a,b) show AFM surface roughness images after 5 μm-thick Ge(111) and Ge(110) deposited with cyclic annealing at 800°C, respectively. Clear terraces of ~0.3 and ~0.2 nm, whose heights are close to those of Ge(111) bilayer and Ge(110) monolayer, are observed, respectively. RMS roughness of the Ge(111) and the Ge(110) are 0.51 and 0.35 nm, respectively. These RMS roughnesses are comparable to a level reported for Ge (001) in ref.(1).Figure 4 shows TDD of Ge(111) and Ge(110) surfaces as a function of the Ge thickness deposited with cyclic annealing on Si(111) and Si(110) substrates. For both orientations, TDD of ~4×108 cm-2 is obtained for 500 nm-thick samples. With increasing the Ge thickness, the TDD is reduced and levels below TDD of ~5×106 cm-2 are achieved for both Ge (111) and Ge(110) for 5 μm-thick Ge.These methods enable high quality virtual substrate fabrication not only for (001) surfaces but also for (111) and (110) orientation without a chemical mechanical polishing process. References Lischke et al. Nature Photonics15 (2021) 925Yamamoto et al. Solid-State Electron. 60 (2010) 2Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 M. Hartmann et al. J. Appl. Phys. 95 (2004) 5905 H. Lee et al. IEDM Tech. Digest (2009) 09-457J-H. Lee et al. Science 344 6181(2014) 286M. Hartmann et al. J. Cryst. Growth 310 (2008) 5287 Figure 1

Strain Modulation of Selectively and/or Globally Grown Ge Layers.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm−2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was −0.34%; meanwhile, the TDD and RMS surface roughness were 2 × 106 cm−2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

Real-time spectro-ellipsometric approach to distinguish between two-dimensional Ge layer growth and Ge dot formation on SiO2 substrates

Morphological evolution of Ge layers on SiO2 substrates grown by photo-excited chemical vapor deposition from GeH4 was monitored in real time by recording (Ψ, Δ) angles of spectroscopic ellipsometry and ex-situ analyzed by atomic force microscopy (AFM). Distinct Ψ-Δ trajectory shapes were demonstrated to discriminate the two-dimensional (2D) and three-dimensional (3D) growth modes. While the trajectory of 2D growth is characterized by a one-turn spiral, that of 3D growth consisted of three sections corresponding to initial wetting of the SiO2 surface, creation of nucleation centers, and dot growth. The critical point where the system turns into 2D or 3D growth can be in situ identified in terms of the directions of the Ψ-Δ trajectories. AFM images revealed characteristic changes in the microstructure, including self-assembling dots and dots merging with one another. While the root-mean-square surface roughness increased linearly against film thickness, the maximum peak-to-valley height deviated once from linear dependence and later returned back to it, which reflected coarsening of dots and embedding of valleys between dots.

Low-temperature growth of fully epitaxial CoFe/Ge/Fe3Si layers on Si for vertical-type semiconductor spintronic devices

We develop a low-temperature growth technique of epitaxial Ge layers on a body-centered-cubic ferromagnetic metal (bcc-FM), Fe3Si, by combining solid phase epitaxy (SPE) and molecular beam epitaxy (MBE). The insertion of an SPE-grown Ge layer enables two-dimensional epitaxial growth of Ge layers by MBE even at a growth temperature of ∼175 C. Thanks to the relatively flat surface of the Ge epilayers, we can obtain an epitaxial CoFe (bcc-FM) layer on top of the Ge layers, leading to the all-epitaxial CoFe/Ge/Fe3Si trilayer with a reasonable magnetization reversal process. We believe that the all-epitaxial CoFe/Ge/Fe3Si trilayer has great potential to be utilized as novel vertical-type Ge-channel spintronic devices.

Growth of germanium on Au(111): formation of germanene or intermixing of Au and Ge atoms?

We studied the growth of Ge layers on Au(111) under ultra-high vacuum conditions from the submonolayer regime up to a few layers with Scanning Tunneling Microscopy (STM), Direct Recoiling Spectroscopy (DRS) and Low Energy Electron Diffraction (LEED). Most STM images for the thicker layers are consistent with a commensurate 5 × 8 arrangement. The high surface sensitivity of TOF-DRS allows us to confirm the coexistence of Au and Ge atoms in the top layer for all stages of growth. An estimation of the Au to Ge ratio at the surface of the thick layer gives about 1 Au atom per 2 Ge ones. When the growth is carried out at sample temperatures higher than about 420 K, a fraction of the deposited Ge atoms migrate into the bulk of Au. This incorporation of Ge into the bulk reduces the growth rate of the Ge films, making it more difficult to obtain films thicker than a few layers. After sputtering the Ge/Au surface, the segregation of bulk Ge atoms to the surface occurs for temperatures ≥600 K. The surface obtained after segregation of Ge reaches a stable condition (saturation) with an n × n symmetry with n on the order of 14.

Large single-crystal Ge-on-insulator by thermally-assisted (~400 °C) Si-seeded-pulse-laser annealing

Low temperature (≤400°C) formation of orientation-controlled large (≥10µm) Ge-on-insulator (GOI) structures is desired to fabricate 3-dimensional large-scale integrated circuits (LSIs), where Ge-based functional devices are stacked on Si-LSIs. For this purpose, Si-seeded pulse-laser annealing (PLA) combined with low-temperature substrate heating (≤400°C) has been developed. Here, a-Ge stripes on Si substrates partially covered with insulating films are subjected to PLA, where single edges of the a-Ge stripes directly contact Si-seeding substrates through opening windows of insulating films. PLA at room temperature generates lateral growth of Ge layers from Si-seeding substrates. However, the growth length is short (~1µm), which is attributed to very short melting time. To increase the melting time, low-temperature (≤400°C) substrate heating during PLA is examined. As a result, very large (~20µm) orientation-controlled GOI is obtained by combining substrate heating (400°C) with PLA. Detailed electron microscopy analysis reveals very high crystallinity of the grown layers. Consequently, high-quality rapid-melting growth of Ge becomes possible at a low processing temperature of ~400°C. This thermally-assisted (~400°C) Si-seeded PLA will facilitate realization of 3-dimensional LSIs.

Mechanisms of Si and Ge diffusion on surfactant terminated (111) silicon and germanium surfaces

Surfactant mediated growth of Ge layers and formation of small Ge clusters on Si(111) are promising assemblage processes with envisioned applications in areas such as nanoelectronics or photovoltaics. They critically depend on migration of Si and Ge adatoms on surfactant terminated Si(111) and Ge(111) surfaces. We address Si and Ge adsorption and migration on surfactant (Bi, Sb) terminated (111) surfaces of Si and strained Ge by comprehensively mapping potential energy surfaces using density functional calculations. The main migration paths are identified and corresponding energy barriers are reported. It is shown that the energy barrier for adatom migration through Bi or Sb surfactant trimers (by actually breaking the trimers) is virtually degenerate to the mechanism involving traveling of the adatom around the same surfactant structures. We also find a low-energy anchoring site that is suggested to act as a nucleation structure and to trigger the clustering process. These results suggest a fundamentally new picture for the whole Si(111)Bi(Sb) epitaxial process.

Enhanced Si–Ge interdiffusion in high phosphorus-doped germanium on silicon

Si–Ge interdiffusion with different P doping configurations was investigated. Significant interdiffusion happened when the Ge layers were doped with P in high 1018 cm−3 range, which resulted in a SiGe alloy region thicker than 150 nm after defect annealing cycles. With high P doped Ge, Si–Ge interdiffusivity is enhanced by 10–20 times in the xGe > 0.7 region compared with the control sample without P doping. We attribute this phenomenon to the much faster P transport towards the Ge seeding layers from the Ge side during the Ge layer growth, which increases the negatively charged vacancy concentrations and thus the interdiffusivity due to the Fermi effect in Si–Ge interdiffusion. This work is relevant to Ge-on-Si type device design, especially Ge-on-Si lasers.

CMOS Compatible Growth of High Quality Ge, SiGe and SiGeSn for Photonic Device Applications

Epitaxial growth of group IV materials on Si has been widely explored for integration of active and passive opto-electronic devices in integrated circuits. In order to meet the limitations imposed by complementary-metal-oxide-semiconductor (CMOS) technology, low temperature growth (below 450 ºC) has been pursued through different methods [1]. Achieving high quality growth at low temperatures is a challenge due to low decomposition rate of SiH4 and GeH4 and lower surface mobilty of adatoms. Propagation of threading dislocations and poor crystallinity of the films deteriorates optical efficiency and electronic transport properties of the film. Reduction of threading dislocation density of the Ge films have been achieved by different methods such as graded SiGe buffer layers, low-temperature:high-temperature (LT:HT) growth of Ge layer and annealing at elevated temperatures [2-4]. In this paper, we report on the role of different carrier gases (Ar, N2 and H2) in LT:HT growth of Ge layers by chemical vapor deposition (CVD) to attain low threading dislocation density (TDD) films. The optimized growth conditions have been applied for the growth of SiGe and SiGeSn films using SnD4 as Sn precursor. Propagation of defects in Ge rich films are mainly due to the threading of the screw dislocation throughout the film. Growth of a sacrificial layer like SiGe or LT Ge, results in reduction of threading dislocation through graded lattice change or merging of the defects [5]. The transport and reactions of the precursors are highly affected by the carrier gas in CVD processes. The carrier gases play a significant role in transferring the energy to the precursor molecules in the gas phase as well as affecting the deposition on the surface [6]. Larger gas molecules have higher cross-section with the precursors to transfer the energy and break the bonds before reaching the surface. On the other hand, presence of hydrogen in the precursor gases cause, the surface of the sample to be covered with hydrogen after the ad-species are bonded with the surface. Hydrogen as carrier gas increases the partial pressure of hydrogen which lowers the adsorption of ad-species to and desorption of byproducts from the surface. Ar or N2 gases lower the partial pressure of hydrogen and change the balance in favor of ad-species adsorption and hydrogen desorption during deposition. This results in a lesser competition between ad-species adsorption and hydrogen desorption. Fig.1 a shows the X-ray diffraction (XRD) patterns of the Ge films deposited using different carrier gases. The growth was performed using a HT:LT mechanism at 300-550 ºC temperature. The results show that Ge growth in Ar ambient has higher quality in comparison with N2 and H2 which is attributed to the larger size of Ar and lower hydrogen partial pressure at the surface. The cross-sectional transmission electron microscopy (TEM) image of growth with Ar ambient shows TDD as low as 1.3×107 cm-2 [Fig.1(b)]. Growth in N2 and H2 show poor quality as seen in the XRD patterns [Fig.1(a)]. SiGe and SiGeSn films were grown using the optimized conditions for Ge growth. A complete study of growth from 0.1 torr to 1 torr, at temperatures from 350-450 ºC for different precursor flow rates is performed. Silicon incorporation in Ge films varied from 1% to 28% for SiGe films [Fig.1(a)]. Tin incorporation of 2% was observed in the films with 13% to 17% Si incorporation [Fig.1(a)]. Investigation of film quality has been done using etch pit measurement with Schimmel solution for 10 minutes. The comparison of TDD using TEM (1.3×107 cm-2) and SEM images (1.7×107 cm-2) for Ge films confirm the accuracy of the measurements. Figs.1 (c), (d), and (e) show the scanning electron microscopy image (SEM) of etch pit Ge, SiGe and SiGeSn films respectively. The TDD of SiGe growth is 2.3 ×107 cm-2 , while the TDD of SiGeSn film is 4.0 ×107 cm-2. Our investigations show that high quality growth of Ge, SiGe and SiGeSn films has been achieved using Ar carrier gas at CMOS compatible temperatures. The material characterization of Ge films show optimized growth condition using Ar carrier gas. Low TDD of SiGe and SiGeSn films show high quality material growth that can be used for optoelectronic device applications.

Lateral Gemanium Growth for Local GeOI Fabrication

Ge is a very attractive material for optoelectronic applications and for future CMOS technologies. Therefore the creation of Ge on Si with low defect density is of great interest. Several techniques to grow high quality Ge on Si are reported e. g. in combination with cyclic annealing and etching (1, 2) or using the aspect ratio trapping technique (3). In this study, the fabrication of local GeOI structures is demonstrated by filling a lateral cavity which was formed by selective sidewall etching (4) of a mesa-patterned SiO2 / Si layer on a SOI wafer. Lateral Ge growth is carried out by using a single wafer reduced pressure CVD system. For sample preparation, epitaxial Si is deposited. The thickness of the Si on buried oxide (BOX) is targeted to 430 nm. Then wet oxidation for 300 nm is performed to produce a 300 nm thick SiO2 cap on top of 300 nm thick Si on the BOX. Top SiO2 and Si on BOX are removed by RIE dry etching to form lateral Si (010) or Si (110) surfaces at the sidewall of a mesa structure. After that, the wafer is cleaned by standard HF-last RCA cleaning. The wafer is loaded into the epi. chamber and baked at 850oC in H2 to remove residual oxide on the Si sidewalls. Then selective etching of Si by HCl is performed to form a cavity in the SiO2. After the HCl etching, Ge is deposited selectively using a H2-GeH4-HCl gas mixture. SEM is used for characterization of the deposited Ge and TEM is applied for dislocation analysis. The strain distribution is analyzed by micro Raman spectroscopy at 514 nm laser wavelength. An angle view SEM image of the sample after HCl etching is shown in Fig. 1. By HCl etching Si between the BOX and the SiO2 cap is laterally removed. The thickness loss of the BOX and the SiO2 cap are negligible indicating that the Si etching process is highly selective to SiO2. No bending is observed at the floating part of the SiO2 cap layer. At the etchfront a Si (111) facet is formed by the lateral HCl etching. A cross section TEM image of the sample after HCl etching and selective Ge growth is shown in Fig. 2. The Ge layer is selectively grown laterally on the Si surface in the cavity formed by the HCl etching. Dislocations are densely located near the interface between Si and Ge. Aspect ratio trapping (3) also works for the lateral direction, resulting in a high crystal quality Ge layer growth after ~200 nm. In Figure 3, an AFM amplitude image of a 5 µm square mesa structure with [010] sidewall direction is shown after HCl etching and lateral Ge growth followed by the removal of the SiO2 cap by HF dip. The interface between Si and Ge is visible. The root mean square of the Ge surface roughness is ~0.4 nm. It is defined by the interface roughness between Si and the SiO2cap layer. In Figure 4, a plan-view TEM image of a 5 µm square mesa structure after HCl etching and lateral Ge growth is shown. A (113) facet is observed at the growthfront of Ge. Dislocation networks are located near the Si interface. Stacking faults run only parallel or perpendicular to the [110] direction. Between them a wide area without any dislocations toward the [010] direction is observed. These results demonstrate the feasibility of the fabrication of local GeOI with high crystal quality by an additional lithography and an etching process. References 1) Y. Yamamoto et al., Solid-State Electronics 60 (2011) 22) Y. Yamamoto et al., Thin Solid Films 520 (2012) 32163) J. S. Park et al., Appl. Phys. Lett. 90 (2007) 0521134) Y. Yamamoto et al. Thin Solid Films 517 (2008) 90

Growth of a Ge layer on 8 in. Si (100) substrates by rapid thermal chemical vapor deposition

We have made the successful growth of Ge layer on 8in. Si (100) substrates by rapid thermal chemical vapor deposition (RTCVD). In order to overcome the large lattice mismatch between Ge and Si, we used a two-step growth method. Our method shows the uniformity of the thickness and good quality Ge layer with a homogeneous distribution of tensile strain and a lower etch pit density (EPD) in order of 105cm−2. The surface morphology is very smooth and the root mean square (RMS) of the surface roughness was 0.27nm. The photocurrent spectra were dominated by the Ge layer related transition that corresponding to the transitions of the Si and Ge. The roll-off in photocurrent spectra beyond 1600nm is expected due to the decreased absorption of Ge.

The microstructure of Ge/Si layers grown at low temperature

Multilayer Si/Ge heterostructures with the thickness of Ge layers varying from 2 to 12 monolayers (ML) were formed by molecular beam epitaxy (MBE) on the (001) Si substrates at 300°C (Ge) and 450°C (Si). The study of the Si/Ge heterostructures was performed by transmission and Cs corrected scanning transmission electron microscopy (STEM). It was shown that the growth of Ge layers up to thickness of 5 ML occurs through the Frank – van der Merwe mechanism. For thicker Ge layers the growth mechanism of the Si-Ge heterostructure changes to Stranski – Krastanov with Si-Ge islands having the shape of inverted pyramids. The Si-Ge layer intermixing was discussed.

Computer Investigations of Features of RHEED Oscillations for GaAs and for Ge

During molecular beam epitaxy regular oscillations of the intensity of the specularly reflected beam often occur. The phenomenon of such oscillations is still theoretically explained only partially. For example it is not clear why usually the oscillation phase depends strongly on the glancing angle of the incident beam. However, quite recently interesting results were shown in the literature on the features of RHEED oscillations observed during the growth of Ge layers. The phase of oscillations practically stays constant for a wide range of angles. So in this paper, we show results of RHEED dynamical calculations for Ge. They are presented together with results of calculations for GaAs to make analysis executed more complete. It is concluded that experimental findings for Ge for off-symmetry azimuths can be explained using dynamical diffraction theory employing the proportional model (for which the scattering potential of the layer is determined as the potential of the completed layer multiplied by the coverage).

The microstructural and optical properties of Ge/Si heterostructures grown by low-temperature molecular beam epitaxy

Abstract

An ultra-thin buffer layer for Ge epitaxial layers on Si

Using an Fe3Si insertion layer, we study epitaxial growth of Ge layers on a Si substrate by a low-temperature molecular beam epitaxy technique. When we insert only a 10-nm-thick Fe3Si layer in between Si and Ge, epitaxial Ge layers can be obtained on Si. The detailed structural characterizations reveal that a large lattice mismatch of ∼4% is completely relaxed in the Fe3Si layer. This means that the Fe3Si layers can become ultra-thin buffer layers for Ge on Si. This method will give a way to realize a universal buffer layer for Ge, GaAs, and related devices on a Si platform.

Nature of contrast in Ge/Si(111) layers in scanning tunneling microscopy in the presence of Bi and Sb surfactants

It is known that the use of Bi surfactant (unlike Sb) upon the growth of Ge layers on Si(111) increases the contrast between Ge and Si atoms in a scanning tunneling microscope. This makes it possible to distinguish the Ge and Si surfaces. This effect is studied using computer simulation based on the density functional theory. To explain the observed difference between the Ge and Si layers, both structural and electronic effects are considered. The local density of electronic states, as well as the corresponding decay length to vacuum, has been calculated for each of the surfaces. The simulation results have been compared to the previous scanning tunneling microscopy data.

Epitaxial growth of relaxed germanium layers by reduced pressure chemical vapour deposition on (110) and (111) silicon substrates

The growth of Ge on (110) and (111) oriented Si substrates is of great interest to enhance the mobility of both holes and electrons in complementary metal oxide semiconductor transistors. However, the quality of thick, relaxed Ge layers grown epitaxially on these surfaces is usually much lower than similar layers grown on (100) Si, resulting in both higher defect densities (i.e. threading dislocations and stacking faults) and rougher surfaces. In this work we have investigated the growth of Ge layers on (110) and (111) Si substrates by reduced-pressure chemical vapour deposition using a two temperature process. We have found that the combination of suppressing the Ge seed layer roughness and high temperature post-growth annealing can reduce the rms surface roughness of (110) Ge layers to below 2nm and the threading dislocation density to below 1×107cm−2. Thick (111) Ge layers were found to exhibit a very high density of stacking faults, that could not be reduced by post-growth annealing and a higher rms surface roughness of around 12nm, which was limited by the Ge seed layer.

Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD

Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 10 8 cm −2 for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 10 5 cm −2 is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.

Features of two-dimensional to three-dimensional growth mode transition of Ge in SiGe/Si(001) heterostructures with strained layers

The results of the study of the effect of strained SiGe layers on the critical thickness of two-dimensional growth of Ge layer in different SiGe/Si(001) structures are presented. A significant influence of buried strained SiGe layer on the growth of Ge has been found out, which remains considerable even for SiGe layers capped by unstrained Si layer of thickness up to 3.5 nm. The experimental results are well described by the proposed model, where obtained features are explained by means of introducing a phenomenological parameter called “effective decay length” of the strain energy accumulated in the structure.