Gate Oxide Growth Research Articles

Effect of Oxide Thickness by Metallic Residue during Radical Oxidation Using Vertical Batch-Type Furnace Equipment on 300-Mm-Diameter Silicon Substrates

Metallic residues have a detrimental effects on device performance as well as retard gate oxide growth rate to induce unintended thinner oxide layer. In this study, we found that oxide thickness could be subjective to metallic residues on the edge of silicon substrate. Hydrogen-assisted radical oxidation was investigated using vertical batch-type furnace equipment for a 300-mm wafer fab. Radical oxidation has been used to improve gate oxide quality overcoming the disadvantages of conventional wet or dry thermal oxidation for some applications. Since the radical oxidation method reduces dangling bonds and defects in the oxide layer due to activated oxygen radicals, a high-quality oxide film can be formed. It also helps improve reliability due to reduced dependence on the silicon crystal direction of oxidation, enabling uniform membrane deposition of stress-focused corner rounding oxidation. In addition, it has excellent throughput as it is possible to process up to 100 wafers simultaneously. This study has shown that as the number of wafers with metallic residues in the dummy pattern on the edge due to the wafer edge exposure (WEE) difference for each photo step increases in the same batch for radical oxidation, the median thickness has decreased. When the silicon wafer with the metallic residue was included within the same batch of the furnace equipment, the thickness of the oxide layer was reduced by 1.8% compared to when the metallic residue-free silicon wafer was included. The radical oxygen have a tendency to react to tungsten rather than silicon, which reduces the O2 value required to form SiO2 and lowers the thickness, which is due to the difference in electronegativity between silicon and tungsten, 1.9 and 2.36 respectively. The study is expected to improve gate oxide quality by controlling metal residues on the wafer edge or backside during the fab process.

Design and Fabrication of 4H-Sic Mosfets with Optimized JFET and p-Body Design

In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO2 and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm-2eV-1 at EC - EIT = 0.21 eV and channel mobility of 19.3 cm2/Vs at VGS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm2 was obtained with hexagonal cell structure which is very consistent with the simulation results.

Thermal Budget Reduction in Triple Gate Oxide Process by Wet Etch Technique

As transistor geometry shrunk and System on Chip (SoC) requirement increased, chips with multiple operation voltages become regular criteria in IC design specification. It means multiple gate oxide thicknesses have to be integrated in semiconductor manufacturing front-end-of-line (FEOL) process. However, process thermal budget will be one of the concerns of transistor electrical performance shift resulted from diffusion of implantation species. In this study, thicker gate oxide (MV) was etched back by wet chemical as thinner gate oxide (I/O) to reduce gate oxide formation thermal budget. However, wet etching rate was degraded after clean and lithograph sequential processes. The oxidant, in wet clean chemical, oxidized silicon dioxide surface Si-H bonding into Si-OH which reacted with Hexamethyldisilazane (HMDS), commonly used as lithography adhesion material, and form an extremely thin Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on gate oxide surface. Fortunately, Trimethylsiloxy monolayer consists of Si-O bonding and Trimethylsilyl group (-Si(CH3)3) and can be easily removed by O2 plasma treatment. To reduce thermal budget, induced from furnace process of gate oxide formation, in triple gate oxide process, I/O gate oxide was obtained by thicker MV gate oxide wet chemical etching back, showed as Figure 1. However, when I/O gate oxide was removed at LV area, showed as Figure 1, step 6, wet etching rate was decreased. Reviewing similar process in I/O area wet etching back process, showed as Figure 1, step 4, the wet etching rate was normal. To figure out why wet etching rate is different between step 4 and step 6 in Figure 1, both 1:200 dilute HF and gas type HF etching rate and etching rate variation percentage with as growth data were collected by blanket silicon dioxide (SiO2) wafer which quality is same as MV gate oxide and result is showed as Table I. Clean is Piranha and SC1, including SPM (sulfuric acid and hydrogen peroxide mixture, H2SO4+ H2O2) and APM (ammonia, hydrogen peroxide and deionized water mixture, NH3+ H2O2+ H2O) process steps. In Table I, 1:200 dilute HF etching rates are normal after clean and after HMDS treatment, respectively. However, once combining clean and HMDS treatment, 1:200 dilute HF etching rate was decreased around 7.2%, but gas type HF etching rate didn’t show the same phenomena. Moreover, additional O2 plasma treatment was added in final step, 1:200 dilute HF etching rate became normal. HMDS is commonly used adhesives between photo resist and coating surface. The mechanism is silylation reaction, showed as Figure 2. HMDS reacted with SiO2 surface hydroxyl group (-OH) and formed Trimethylsiloxy monolayer (Si-O-Si(CH3)3) on SiO2 surface which changing surface property from hydrophilic into hydrophobic. Adhesion between Photo resist and SiO2 surface had been improvement due to the enhancement of van der Waals’ force. Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation amount depends on hydroxyl group (-OH) amount on SiO2 surface. From Table II, after clean process, SiO2 surface hydroxyl group (-OH) increase due to the existence of hydrogen peroxide in clean chemical. The SiO2 surface become more hydrophilic, water contact angle decreased from 35.3° to 14.8°. After HMDS priming, SiO2 surface hydroxyl group (-OH) were substituted by Trimethylsiloxy group (-O-Si(CH3)3). The SiO2 surface become hydrophobic, water contact angle increased from 35.3° to 52.2°. After combining clean and HMDS processes, the water contact still increased from 52.2° to 59.1°. It means after clean process, some Si-H bondings oxidized by hydroperoxide into hydroxyl group (-OH), which will increase final Trimethylsiloxy monolayer (Si-O-Si(CH3)3) amount on SiO2 surface. After O2 plasma process, SiO2 surface was back to as growth condition by compatible water contact angle result. Reviewing Table I data, 1:200 dilute HF etching rate dropped main root cause is the existence of Trimethylsiloxy monolayer (Si-O-Si(CH3)3). The densification of this monolayer might be not as good as from deposition process and results in gas type HF can easily penetrate to bottom oxide layer and no etching rate was impacted. Fortunately, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be removed by O2 plasma treatment. To replace one of triple gate oxide growth under high temperature by thicker gate oxide wet etching back process. Post etched clean step and HMDS in following step will interfere with dilute HF etching behavior due to Trimethylsiloxy monolayer (Si-O-Si(CH3)3) formation. By adding additional O2 plasma treatment, Trimethylsiloxy monolayer (Si-O-Si(CH3)3) can be easily and successfully removed and wet dilute HF SiO2 etching rate was back to normal. The thermal budget of triple gate oxide process can be successfully reduced by gate oxide wet etching back technique. Figure 1

Single-Grain Si Tfts Fabricated on a Precursor from Doctor-Blade Coated Liquid-Si

In the application of display, Si TFTs is superior than organic TFTs and metal oxide TFTs in the sense of carrier mobility, reliability and traditional IC process compatibility. However, the difficulty of achieving single crystalline Si limits the application of Si TFTs. In this paper, we would like to present a low-temperature approach for manufacturing single-grain Si TFTs on a precursor from doctor-blade coated liquid-Si on flexible polyimide substrate, with the carrier mobility of 460 cm2/Vs and 121 cm2/Vs, for electrons and holes respectively.Pure cyclopentasilane is used as liquid-Si, and it was coated using doctor-blade method, and polymerized under the UV lamp. According to [1], polysilane was formed after polymerizing the solution of cyclopentasilane and toluene. After an annealing process at 350 °C, an a-Si precursor was formed (see Fig. 1). A XeCl laser with the wavelength of 308 nm was used for the crystallization of the a-Si precursor, and thanks to the special cavity structures called the grain-filters, which are 110 nm width by 700 nm depth, underneath the a-Si layer, Si single grains were formed[2] (see Fig.2). A top-gated transistor was fabricated using the IC-compatible process of ICP gate oxide growth (250 °C), PECVD TEOS oxide (350 °C), Al gate and contact pads formation, self-aligned source-drain dopant ion-implantation and laser activation of the dopants (room temperature). The process temperature was so low that the devices were fabricated on top of flexible polyimide substrate. At the end of the process, all the devices were peeled off from the supporting Si wafer to a PEN foil and become flexible (Fig. 5).The devices show transfer characteristics with high on-off ratio and high carrier mobility, 420 cm2/Vs for electrons and 121 cm2/Vs for the holes (Fig. 3). After peeling off from the Si wafer, the devices could function until a bending diameter of 6 mm (Fig.4). To restrain the mobility degradation during the bending, a double-sided polyimide structure was investigated.[1] T. Shimoda, Y. Matsuki, M. Furusawa, T. Aoki, I, Yudasaka, H. Tanaka, H. Iwasawa, D. Wang, M. Miyasaka and Y. Takeuchi, Nature 440, 6, 2006, 783-786[2] R. Ishihara, P.C. van der Wilt , B.D. van Dijk , A. Burtsev , J.W. Metselaar and C.I.M. Beenakker, Thin Solid Film 427, 2003, 77-85

Extensive Study of the Correlation between Contact Etch Stop Nitride film Properties and Negative Bias Temperature Instabilities Measured in pMOSFETS

Mobility enhancement by process induced strain in the Si channel has been extensively used since 90nm node to improve transistor drive current. Such technique becomes mandatory to compensate scalability limits of several processes like ultra thin gate oxide growth. The Contact Etch Stop nitride Layer (CESL) is the most commonly used method to get stress induced mobility enhancement. However, the re-engineering of this nitride layer for stress enhancement needs to cover all electrical aspects including reliability characteristics, in particular the Negative Bias Temperature Instabilities (NBTI). In this work, we confirm that pMOS NBTI can be significantly impacted by the nitride CESL properties. A Design Of Experiment methodology allows demonstrating that the NBTI is enhanced by the nitride weight density, linked to hydrogen diffusivity within the film. It is finally shown that the nitride density must be set as low as possible to minimize the NBTI.

N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis

This paper presents oxide trap characterization of nitrided and non-nitrided gate oxide N-MOSFETs using low frequency noise (LFN) measurements. The identification of defects generated by the gate oxide growth and the nitridation process is carried out using random telegraph signal noise analysis. Significant properties of traps induced by the nitridation process are pointed out. Main trap parameters, such as their nature, capture and emission times, cross-sections, energy levels, and position with respect to the Si/SiO 2 interface, are extracted. These results illustrate the potential of noise investigation for oxide characterizations.

In-Line Monitor Introduction to Prevent Metallic Contamination in Wet Bench

Contamination controls are very important issues in microelectronics. Any wrong substance introduction in process chambers can cause damages to the production line. Therefore, an extensive control is important because every operation in the process flow (also the most insignificant) can become fatal for the correct functioning of a microelectronic device. The aim of this work is to evaluate the impact of small metallic contamination in the range of 1011÷1012 at/cm2 on silicon substrates implanted with different ion species (As, B and P). An important example of failure related to metallic contamination in a wet bench is reported in this work. The problem appears in a particular class of flash memory devices processing. The electrical parametric test shows a wrong gate oxide thickness and Qbd values out of range, confirmed by early breakdown events and anomalous C-V characteristics. The cause of the failure is morphologically identified off-line by using TEM: the cross section shows a wrong gate oxide thickness and an anomalous interface between gate oxide and silicon substrate. It appears clear that the root failure cause is related to the ion implantation (As in this case) and to the cleaning before gate oxide growth. A short process flow was performed and analyzed step by step in order to identify the failure cause. Many different analytical techniques have been used for each step and all of these provide consistent results. In particular TXRF analysis on wafers processed immediately after cleaning do not show any contamination while Cu and Fe contaminants are observed after sample oxidation and As implant. Metallic contaminants are captured by the substrate after it is implanted with As, and the following RCA cleaning is not able to remove them. In addition, the presence of these metallic contaminants induces roughness of the Si surface and the growth of gate oxide is not controlled (faster oxidation). If different substrates are used, e.g. silicon implanted with B or un-implanted, this contamination level is not detected and does not lead to oxide reliability problems. Once the mechanism of metal contaminant interaction with dopant is identified the introduction of an in-line monitoring is possible, thus allowing to prevent the device failure. The short process loop can be considered as a good method to prepare the substrate before TXRF analysis. After this study the monitor has been integrated in the production line controls

MOS-Junction-Based Nanostructures by Thermal Oxidation of Silicon Wires for Hydrogen Detection

Heavily p-doped monocrystalline silicon wires have been fabricated by employing isotropic Si wet etch and thermal oxidation to achieve a nanometric cross section-a gate-oxide growth and a final palladium evaporation made up the MOS junction able to detect hydrogen concentration in air. Several types of wire dimensions have been designed and fabricated: length ranges from 5 to 70 /spl mu/m; the smallest widths obtained are around 250-300 nm, while the biggest are up to 7 /spl mu/m. Preliminary experimental results show a high signal/noise ratio sensor response to 100 ppm concentration of H/sub 2/ at room temperature, 1-atm air.

Laser induced oxidation for growth of ultrathin gate oxide

A novel technique for the growth of ultrathin SiO2 at room temperature using a pulsed laser has been demonstrated. It is observed that, after an initial high growth rate, the oxide thickness reduces with time and the quality of the oxide improves. The results of our experiments show that this technique can be used to grow high quality ultrathin SiO2 films with excellent control suitable for ULSI MOSFETs.

Suppression of stress-induced leakage current after Fowler-Nordheim stressing by deuterium pyrogenic oxidation and deuterated poly-Si deposition

Reports on the effect of deuterium incorporation into gate oxide on stress-induced leakage current (SILC) under Fowler-Nordheim (F-N) electron injection. Deuterium atoms were introduced during the growth of the gate oxide by deuterium pyrogenic oxidation. A deuterated poly-Si film was also utilized as a gate electrode. The deuterated poly-Si gate electrode was deposited by deuterated monosilane (SiD/sub 4/) gas, as a substitute for hydrogenated monosilane (SiH/sub 4/) gas. The properties of the deuterated oxide were compared with those of deuterium-annealed oxide, i.e., the conventional method for deuterium incorporation into gate oxide. As a result, it was found that SILC after both polarities of F-N stressing was clearly suppressed by the use of both the deuterium pyrogenic oxide and the deuterated poly-Si gate. Experimental results for the depth profiles and thermal desorption characteristics of introduced-deuterium atoms, compared with the case of the deuterium annealing, indicated that both the deuterium incorporation not only into the Si/SiO/sub 2/ interface but also into bulk-SiO/sub 2/ and the more stable chemical bonding of deuterium atoms are realized by deuterium pyrogenic oxidation.

Effect of barium contamination on gate oxide integrity in high-k dram

Barium impact on the gate oxide breakdown was studied using E-ramp and constant current stress (CCS) charge to breakdown. Wafers were contaminated with Ba after a 7.5 nm gate oxide growth and 300 nm poly-silicon deposition. The measurements were done on capacitors having areas of 0.1, 1, 4, and 16 mm2. Up to a contamination level of 4×1014 atoms/cm2 no degradation in oxide integrity was observed either by E-ramp or CCS. Time of flight (ToF)-SIMS measurement of Ba diffusion profile at 800 °C shows a diffusion of Ba over distances of some tens of nanometers, thus Ba does not reach the gate oxide region. The effect on the gate oxide breakdown can be correlated with the slow diffusion of Ba in poly-Si. Therefore, no major concern of yield and reliability due to Ba contamination is seen for the integration of Ba containing dielectrics into memories.

Activation of group III combinations in silicon and modifications introduced by nitrogen

A series of experiments were initiated after finding that a supersteep retrograde channel of an n-channel silicon-based field effect transistor would not have an acceptable threshold voltage if created with indium and sufficient nitrogen (4×1014/cm2) present to retard gate oxide growth. A set of combinations of indium, boron, and nitrogen and a set of combinations of gallium, boron, and nitrogen were examined. It was found that nitrogen caused minimal reduction in the electrical activity of boron, greater reduction with indium, and greatest reduction with indium plus boron. Similar results, though of lesser magnitude, were observed with the gallium set. The chemical profiles of the various dopants in combination with each other gave no indication of the active carrier profile associated with each combination. Theoretical criteria were formulated to attempt to correlate atomic level configurations with electrical activity. Ab initio pseudopotential calculations using the Vienna Ab initio Simulation Package followed; the theoretical criteria correlated very well with the observed electrical activity of the various combinations and, to a lesser degree, with the ordering of nitrogen retention as a function of those combinations. The calculations appear to demonstrate the presence of long range interactions.

Effects of nitridation in gate oxides grown on 4H-SiC

Experiments have demonstrated that nitridation provides critically important improvements in the quality of SiO2–SiC interface. This article provides results and analysis aimed at developing the much needed understanding of the mechanisms and effects associated with both annealing of pregrown oxides and direct growth in NO and N2O environments. According to the model proposed in the article, nitridation plays a double role: (1) creation of strong Si≡N bonds that passivate interface traps due to dangling and strained bonds, and (2) removal of carbon and associated complex silicon–oxycarbon bonds from the interface. This understanding of the effects of nitridation is experimentally verified and used to design a superior process for gate oxide growth in the industry-preferred N2O environment.

Reliability of thin oxides grown on deuterium implanted silicon substrate

We have investigated the reliability of gate oxide with deuterium incorporated at the Si/SiO/sub 2/ interface through low energy ion implantation into the silicon substrate before thin gate oxide growth. Deuterium implantation at a dose of 1/spl times/10/sup 14//cm/sup 2/ at 25 keV showed improved breakdown characteristics. Charge-to-breakdown seems to correlate well with the interface state density measured by the conductance method.

The dependence ofUMOSFET characteristics and reliability on geometry andprocessing

We have examined the impact of trench processing and trench anddevice cell geometries on the characteristics of a singlen-channel U-shaped trench metal-oxide-silicon field-effecttransistor (n-UMOSFET) and a device cell comprising severaln-UMOSFETs. The geometrical parameters investigated includedthe trench depth and width, the trench cross-section and thedevice cell pitch. We have found out that the geometry does notaffect the electron mobility in the channel; however, theeffects of the geometry on the characteristics of the isolateddevice or device cell are manifested on the spreading resistance of thedrain end. Trench processing, in the form of trench etching,trench cleaning and subsequent gate-oxide growth, is observed toprimarily influence the n-UMOSFET's immunity to electricalstress, which is studied using charge pumping current andgate-oxide breakdown measurements. It is shown that thegate-oxide edge adjacent to the drain and the oxide/siliconinterface overlapping the drain are the regions most susceptibleto degradation by Fowler-Nordheim stress. Theseobservations coupled with results from scanning electronmicroscopy suggest that the gate-oxide growth non-uniformity aswell as its condition at the trench corners are the key factorsin determining the n-UMOSFET's reliability.

Electron mobility enhancement in strained SiGe vertical n-type metal–oxide–semiconductor field-effect transistors

We have fabricated strained SiGe vertical n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 μm without sophisticated lithography and the whole process is compatible with a regular complementary metal–oxide–semiconductor process. The drive current for these devices has been observed to be enhanced by 50% compared with Si control devices on the same wafer. Electron mobility enhancement in the out-of-plane direction for the strained SiGe layer was demonstrated in this study.

Impact of platinum contamination on ferroelectric memories

The impact of platinum contamination on the breakdown properties of gate oxide is reported. Wafers were intentionally contaminated with 1×1013 to 4×1014 at/cm2 Pt after a 7.5 nm gate oxide growth, 300 nm poly-silicon deposition and subsequent phosphorus doping. Breakdown characteristics were evaluated using a voltage ramp method. The current-voltage curves of MOS capacitors show very few low field breakdown events, and the main field breakdown occurs at 12 MV/cm. If compared to clean wafers, platinum does not increase the defect density seriously. It is found from the E-Ramp results that platinum contamination up to 4×1014 at/cm2 does not have a pronounced effect on the gate oxide integrity if the contamination occurs after front-end-of-line processing of device fabrication.

Hole and electron mobility enhancement in strained SiGe vertical MOSFETs

We have fabricated strained SiGe vertical P-channel and N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 /spl mu/m without sophisticated lithography and the whole process is compatible with a regular CMOS process. The enhancement for the hole and electron mobilities in the direction normal to the growth plane of strained SiGe over that of bulk Si has been demonstrated in this vertical MOSFET device structure for the first time. The drain current for the vertical SiGe MOSFETs has been found to be enhanced by as much as 100% over the Si control devices and the drain current for the vertical SiGe NMOSFETs has been enhanced by 50% compared with the Si control de, ices on the same wafer. The electron mobility enhancement in the normal direction is not as significant as that for holes, which is in agreement with theoretical predictions.

Ultrathin gate oxide grown on nitrogen-implanted silicon for deep submicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0/spl times/10/sup 14//cm/sup 2/ and 2.0/spl times/10/sup 14//cm/sup 2/. Initial O/sub 2/ injection method was applied for gate oxidation. The method is composed of an O/sub 2/ injection/N/sub 2/ anneal/main oxidation, and the control process is composed of a N/sub 2/ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 /spl mu/m have been fabricated by use of the method. Compared to the control process, the initial O/sub 2/ injection process increases the amount of nitrogen piled up at the Si/SiO/sub 2/ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved.

Diffusion of Implanted Nitrogen in Silicon at High Doses

ABSTRACTNitrogen implantation is used to retard gate oxide growth thereby making it particularly usefulfor dual- VT and System On A chip technologies. This paper discusses the diffusion behavior and the concomitant defect evolution at high doses of implanted nitrogen in silicon. This paper shows that as the nitrogen implant dose is increased, the extent of nitrogen diffusion reduces. This paper also reports based onTEM studies, that upon annealing at 750°C, 5 × 10014 N2+/cm2, 40 keV implant produces Type I extended defects. However, 2 × 1015 N2+/cm2, 40 keV implant, produces a continuous amorphous layer to a depth ofabout 800 to 900 Å from the surface. In addition, upon annealing at 750°C, the 2 × 1015 N2+/cm2, 40 keV implant produces Type V or solid solubility defects in addition to End of Range or Type II defects.