Power devices electronics based on Silicon Carbide (SiC) are emerging as a breakthrough technology for various applications. The link between the quality of SiC substrates and device performance has been widely discussed [1]. Smart Cut™ technology offers the opportunity to integrate a high quality SiC layer on a low resistivity handle wafer. Moreover the crystal quality of a single donor wafer can be replicated multiple times to provide an epitaxy-ready substrate in high volume [2]. Nevertheless, some extended grown-in defects of SiC starting material, like micro-pipes or bulk inclusions, may generate surface defects called "Crystal Originated Defects" (COD) on transferred layers. This paper explains how SmartSiC™ defect density can be reduced by limiting the number of extended defects on donor wafers. Specific inspection recipes were developed to monitor the starting material and the replicated engineered substrate: COD root-causes and effects were analyzed. We demonstrated how a well-suited quality control of donor wafers plays a major role to guarantee defect-free SmartSiC™ wafers.
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