Several process-related interconnect parasitic effects are investigated for standard CMOS 0.35 and 0.25 μm, with the help of PATRICE, a 2D electromagnetic field solver developed by the Grenoble university laboratory LEMO. The effects of the barrier layers and of a slightly trapezoidal cross-section on line resistance and capacitance are studied. The capacitance increase linked to an underlying nitride layer is also evaluated, as well as the influence of the passivation process on capacitances. A set of four interconnection schemes is proposed to reduce parasitic ground and coupling capacitances and thus enhance technology performance. These strategies consist of: increasing the intermetal dielectric (IMD) thicknesses, using SiOF instead of SiO 2, embedding the lines in a low-permittivity dielectric, and switching to copper metallizations with constant line resistance. The effectiveness of these schemes is checked for the capacitances of simple 2D structures and for delay, crosstalk and consumption in typical circuit routings.