Grid Routing Research Articles

A combinatorial congestion estimation approach with generalized detours

Congestion estimation plays an important role in the physical layout of VLSI design. This paper presents a new probabilistic estimation model that improves the previous estimators by relaxing the constraint on detours in a route. The model is more general and realistic for it gives the flexibility for the wires to have wider usage area to bypass the congestion regions and blockages. Given a routing grid and a set of nets to be routed, the model predicts the routing density on each edge of the grid. The routing density provides direct congestion estimation. We compare our estimation results to the actual routing results. Experimental results show the effectiveness of our estimator.

Rearrangeability of bit permutation networks

In this paper, we introduce the concept of routing grid as a tool for analyzing realizability of permutations on bit permutation networks (BPNs). We extend a result by Linial and Tarsi which characterizes permutations realizable on shuffle-exchange networks to any BPNs. A necessary condition for a BPN to be rearrangeable is given, and the rearrangeability of two families of BPNs are explored. Finally, we present a method which may help to tackle one kind of balanced matrix problems whose solution implies an answer to Benes conjecture. Hopefully, our treatment brings some new insight into the problem of permutation routing.

Equidistance routing in high-speed VLSI layout design

In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. In this paper, we propose L-equidistance routing, which routes the concerned nets with a prescribed length L. After a basic technique of L-equidistance routing of a single 1-sink net, an algorithm is presented for the channel routing of plural multi-sink nets. The key idea is in the symmetric-slant grid interconnect scheme by which the problem is reduced to a grid routing problem. In L-equidistance routing of a channel, the total length of a n-sink net is not unique for n⩾3. An algorithm based on dynamic programming to solve this minimization problem is presented. Then, L-equidistance switch-box routing is discussed based on the L-equidistance channel routing. Algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the Manhattan grid is possible keeping the property of equidistance. The proposing channel routing algorithm was implemented and applied to random data to demonstrate their ability.

Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the individual layer's routing grid space, coupling effects such as crosstalk noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.

Compact Routing In Chordal Grids And Other Networks

Static routing based on routing tables is often used in distributed systems. Such a technique becomes inefficient when the networks is big and when an update of the tables is necessary due to a change of the topology. Moreover, this technique is very sensitive to failures and, thus, not fault-tolerant. This paper proposes a routing method which reduces the space complexity and avoids the need of updating all the nodes in wireline networks when changes in the topology occur. Based on a certain labelling of the nodes, this method stores information on the routers, which do not depend on the topology, and is particularly efficient when the network reconfiguration consists of adding and removing nodes.

Wire packing - a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution

By focusing on chip-wide slices of the global routing grid, making a few mild geometric assumptions about layer use, and suitably abstracting pin details, we derive an efficient integer linear programming formulation for track/layer assignment. The key technical insight is to model all constraints both geometric and crosstalk - as cliques in an appropriate conflict graph; these cliques can be extracted quickly from the interval structure of wires in a slice. We develop a "strong" linear relaxation of this problem that almost always yields the integral optimum; this solution gives us directly the maximum number of wires that can be packed legally without crosstalk risk. Experiments on synthetic netlists that match statistics of wire layouts from industrial 0.25-/spl mu/m designs demonstrate that we can pack 100-1000 wires optimally or, at worst, a very few overflows in seconds.

Timing- and crosstalk-driven area routing

We present a timing- and crosstalk-driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative way. The new approach fits between global routing and detailed routing along the physical design flow. It is the first to address the timing- and crosstalk-driven area routing problem using crosspoint assignment prior to the detailed routing stage, in contrast to the most previous approaches applied in the post-detailed routing stage. Our new approach enjoys a larger optimization solution space than the previous approaches whose solution space is highly limited by routed geometric constraints. Based on the global routing information, our graph-based optimizer preroutes wires on the global routing grids incrementally. The graph-based optimizer has two stages, net order assignment and space relaxation. A quick capacitance extraction and Elmore delay calculator considering signal switching activities are implemented to find the timing of critical nets and to provide the timing slack database of critical nets. As the graph-based algorithm proceeds, the path delay of critical nets and the timing slack database are updated. During the optimization process, it only optimizes the timing critical paths with negative slack values. The experimental results show a 5%-16% delay reduction for MCNC macrocell benchmark circuits for a 0.25 /spl mu/m process for wire geometric ratio (height/width)=1.0, against a 25% delay reduction if there is infinite space around each metal wire on the same layer.

GRID: A Fully Location-Aware Routing Protocol for Mobile Ad Hoc Networks

A mobile ad hoc network (MANET) is one consisting of a set of mobile hosts capable of communicating with each other without the assistance of base stations. One prospective direction to assist routing in such an environment is to use location information provided by positioning devices such as global positioning systems (GPS). In this paper, we propose a new routing protocol called GRID, which tries to exploit location information in route discovery, packet relay, and route maintenance. Existing protocols, as compared to ours, are either not location-aware or partially location-aware in that location knowledge is not fully exploited in all these three aspects. One attractive feature of our protocol is its strong route maintenance capability --- the intermediate hosts of a route can perform a "handoff" operation similar to that in cellular systems when it roams away to keep a route alive. This makes routes in the MANET more stable and insensitive to host mobility. Simulation results show that our GRID routing protocol can reduce the probability of route breakage, reduce the number of route discovery packets used, and lengthen routes' lifetime.

Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to minimize crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. We present a simulated annealing approach based on segment rearrangement to crosstalk minimization in an initially gridded channel routing. The proposed technique is compared with previous track-oriented techniques, especially a track permutation technique whose performance is bounded by an exhaustive track permutation algorithm. Experiments showed that the presented technique is more effective than the track permutation technique.

A fast multilayer general area router for MCM designs

An efficient multi layer general area router is developed as an alternative to the 3-D maze router for solving the multi-layer multichip module (MCM) routing problem. The router, named SLICE, is independent of net ordering, requires much shorter computation time, and uses fewer vias. A key step is to compute a maximum noncrossing bipartite matching, which is solved optimally in O(n log n) time where n is the number of possible connections. The router was tested on a number of examples, including two MCM designs from MCC. The total wirelength used by SLICE is only a few percent away from the optimal on average. Compared with a 3-D maze router, SLICE is six times faster and uses 29% fewer vias. Another feature of SLICE is that it works on only a 'thin slice' of a two-layer routing grid at a time, so it can produce solutions for large MCM routing examples where 3-D maze routers fail due to insufficient memory.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Maze routing on a hypercube multicomputer

The implementation of Lee's maze routing algorithm on an MIMD hypercube multiprocessor computer can follow several plausible mappings and synchronization strategies. These are evaluated experimentally on an NCUBE/7 hypercube computer with 64 processors. Different grid partitioning and mapping strategies result in a different balance between computation and communication time. The total routing time is significantly impacted by the synchronization and termination detection scheme used. Further, by rearranging the computation, it is possible to overlap much of the interprocessor communication with the computation and realize a significant reduction in the overall run time. By choosing the right partitioning and synchronization scheme and by overlapping computation and communication, a good speedup is obtained on large routing grids.

Systolic routing hardware: performance evaluation and optimization

The performance of maze-routing algorithms mapped onto linear systolic array hardware is examined. Cell expansions in the wavefront-expansion phase of maze routing are performed in parallel in each processing stage of the hardware as the routing grid streams through the processor array. The authors concentrate on optimizing the performance of single-net routing problems with respect to a given systolic hardware configuration. A heuristic called constant-increment framing is introduced as a simple method for scheduling all the required wavefront expansion steps on a pipeline of processors. One-layer and two-layer routers using this heuristic have been implemented on a prototype systolic processor. Experimental and theoretical comparisons suggest that the constant-increment heuristic exhibits performance within a factor of two of optimal over a range of hardware configurations, and is substantially easier to compute than the optimal solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Class of Array Architectures for Hardware Grid Routers

Special-purpose hardware architectures have been recently proposed for solving a number of increasingly complex design automation problems. This paper proposes a class of two-dimensional SIMD array processors--the IAP architectures for implementation of grid routing algorithms. The major advantages of the IAP machines are, completely modular designs which are not pin-limited regardless of array size, and the ability to find the lowest cost route for a net, in time which is a linear function of the length of that route. A number of new procedures for parallel routing (simultaneous routing of k nets) are introduced, which take advantage of the linear time complexity of the IAP architectures. An analysis is presented of the time complexities of these procedures and examples are presented to exhibit their applicability.