Graded Doping Profile Research Articles

Nanoscale Graded Nitrogen-Doping of TiO2 via Pulsed Laser Deposition for Enhancing Charge Transfer in Perovskite Solar Cells.

An electron transport layer (ETL) for highly efficient perovskite solar cells (PSCs) should exhibit superior electrical transport properties and have its band levels aligned with interfacing layers to ensure efficient extraction of photo-generated carriers. Nitrogen-doped TiO2 (TiO2:N) is considered a promising ETL because it offers higher electrical conductivity compared to conventional ETLs made from spray-pyrolyzed TiO2. However, the application of highly doped TiO2:N in PSCs is often limited by the misalignment of energy band levels with adjacent layers and reduced optical transparency. In this study, a novel approach is introduced to enhance the charge transport characteristics and accurately align the electronic band alignment of TiO2:N layer through nanoscale doping level grading, achieved through the pulsed laser deposition (PLD) technique. The TiO2:N ETL with a graded doping profile can combine characteristics of both highly doped and lightly doped phases on each side. Furthermore, a nanoscale doping gradation, employing an ultrathin sub-layer structure with graded doping levels, creates a smoothly cascading band-level alignment that bridges the adjacent layers, enhancing the transport of photo-generated carriers. Consequently, this method leads to a substantial increase in the power conversion efficiency (PCE), exceeding 22%, which represents a relative improvement of 11% compared to traditional spray-pyrolyzed TiO2-based PSCs.

Undoped Drain Graded Doping (UDGD) based TFET design: An innovative concept

The work deals with the implementation of charge plasma concept towards the formation of graded doping profile in the Drain region of Tunnel FET (TFET) device architecture. This new and innovative concept of graded doping profile in the lateral direction holds its merit towards stopping the ambipolar conduction in TFETs without affecting its off and the on state performance. The proposed device i.e. Undoped Drain Graded Doping based TFET (UDGD TFET) architecture is highly effective in suppressing the gate to drain and therefore the total gate capacitance values and thus also seems promising towards reduction in the dynamic power dissipation in TFETs. The architecture has also shown significant improvements for RF application in terms of cut-off frequency, Gain Bandwidth and Transit Time with optimized parameters such as gate work function, drain workfunction, channel length and drain region length when compared to conventional Tunnel FETs.

Multizone Gradient-Modulated Guard Ring Technique for Ultrahigh Voltage 4H-SiC Devices With Increased Tolerances to Implantation Dose and Surface Charges

An area efficient multizone gradient-modulated guard ring (MGM-GR) edge termination technique is proposed, fabricated, and analyzed for 10-kV class silicon carbide devices without extra process steps or masks, which provides a better tradeoff between near ideal blocking capabilities and technological process complexity. The edge termination region is divided into multiple zones by employing MGM-GR technique, which forms a similar linearly graded doping profile to relieve the amount of electric field crowding at the periphery of the active area and achieve a maximum blocking voltage with wide tolerance to implantation dose. The proposed device shows not less than a 35% reduction in edge termination area in comparison with a conventional equally spaced ring at a breakdown voltage of 10 kV. Moreover, MGM-GR shows good tolerances to breakdown voltage for total implant dose and interface charges. With the application of MGM-GR technique to SiC MOSFET with a 100- $\mu \text{m}$ -thick N− epilayer doped to $5 \times 10^{14}$ cm $^{-3}$ , the measured breakdown voltage is 13.6 kV at $10~\mu \text{A}$ . This voltage is nearly 95% of the theoretical value calculated for a 1-D structure. Simulated and measured characteristics show that MGM-GR structure is a candidate for an ultrahigh voltage power device to maximize power density and driving down system complexity.

Current Gain Degradation Model of Displacement Damage for Drift BJTs

Drift bipolar junction transistors (BJTs), characterized by a graded doping profile in the base region, are susceptible to the recombination in both the base and emitter–base depletion regions when they are damaged by atomic displacement, leading to the gain degradation. The previous model of the gain degradation of BJTs (i.e., Messenger–Spratt model) adopts the assumptions of the neutral base and ideal depletion, which are not valid for the drift BJTs. A drift BJT has an extra build-in electric field which breaks the neutral base condition, and the excess recombination rate is reduced and depends on the drift parameters. Furthermore, the nonideal depletion effects can suppress the excess recombination in the junction region, which will also reduce the susceptibility of the displacement damage (DD). This paper presents a physics-based improvement of the previous model and provides a much better fit to the experimental data of the 3CK3B drift BJTs subjected to deuterium–tritium 14-MeV neutron irradiation. The new model also suggests that the ideal factor of excess base current induced by DD approaches to 1.33 for the BJT technologies with narrow base or operated under low bias conditions.

Shortening turn-on delay of SiC light triggered thyristor by 7-shaped thin n-base doping profile**Project supported by the National Natural Science Foundation of China (Grant No. 51677149).

A new 4H–SiC light triggered thyristor (LTT) with 7-shaped thin n-base doping profile is proposed and simulated using a two-dimensional numerical method. In this new structure, the bottom region of the thin n-base has a graded doping profile to induce an accelerating electric field and compensate for the shortcoming of the double-layer thin n-base structure in transmitting injected holes. In addition, the accelerating electric field can also speed up the transmission of photon-generated carriers during light triggering. As a result, the current gain of the top pnp transistor of the SiC LTT is further increased. According to the TCAD simulations, the turn-on delay time of the SiC LTT decreases by about 91.5% compared with that of previous double-layer thin n-base SiC LTT. The minimum turn-on delay time of the SiC LTT is only 828 ns, when triggered by 100 mW/cm2 ultraviolet light. Meanwhile, there is only a slight degradation in the forward blocking characteristic.

Multiple Schottky Barrier-Limited Field-Effect Transistors on a Single Silicon Nanowire with an Intrinsic Doping Gradient.

In comparison to conventional (channel-limited) field-effect transistors (FETs), Schottky barrier-limited FETs possess some unique characteristics which make them attractive candidates for some electronic and sensing applications. Consequently, modulation of the nano Schottky barrier at a metal-semiconductor interface promises higher performance for chemical and biomolecular sensor applications when compared to conventional FETs with ohmic contacts. However, the fabrication and optimization of devices with a combination of ideal ohmic and Schottky contacts as the source and drain, respectively, present many challenges. We address this issue by utilizing Si nanowires (NWs) synthesized by a chemical vapor deposition process which yields a pronounced doping gradient along the length of the NWs. Devices with a series of metal contacts on a single Si NW are fabricated in a single lithography and metallization process. The graded doping profile of the NW is manifested in monotonic increases in the channel and junction resistances and variation of the nature of the contacts from ohmic to Schottky of increasing effective barrier height along the NW. Hence multiple single Schottky junction-limited FETs with extreme asymmetry and high reproducibility are obtained on an individual NW. A definitive correlation between increasing Schottky barrier height and enhanced gate modulation is revealed. Having access to systematically varying Schottky barrier contacts on the same NW device provides an ideal platform for identifying optimal device characteristics for sensing and electronic applications.

Gate-Tunable Spatial Modulation of Localized Plasmon Resonances.

We demonstrate localization and field-effect spatial control of the plasmon resonance in semiconductor nanostructures, using scattering-type scanning near-field optical microscopy in the mid-infrared region. We adopt InAs nanowires embedding a graded doping profile to modulate the free carrier density along the axial direction. Our near-field measurements have a spatial resolution of 20 nm and demonstrate the presence of a local resonant feature whose position can be controlled by a back-gate bias voltage. In the present implementation, field-effect induces a modulation of the free carrier density profile yielding a spatial shift of the plasmon resonance of the order of 100 nm. We discuss the relevance of our electrically tunable nanoplasmonic architectures in view of innovative optoelectronic devices concepts.

Solution p-doped fluorescent polymers for enhanced charge transport of hybrid organic-silicon nanowire photovoltaics

The solution p-type doping of various conjugated polymers and small molecules via blending with tetrafluorotetracyano-quinodimethane (F4-TCNQ) is investigated to facilitate hole transport for hybrid organic-silicon-nanowire solar cells. Among all, the highly-fluorescent conjugated polymers such as poly(9,9-dioctylfluorenyl-2,7-diyl) (PFO) demonstrate superior transport characteristics, where both the device fill-factor and power conversion efficiency (PCE) are positively correlated with the doping concentration. The best PCE achieves 13.66% from the device with 30% p-doped PFO, compared to the reference at 12.50%. The enhancement is ascribed to the efficient interfacial charge-carrier recombination with minimal energy losses. A vertically graded doping profile is further revealed with F4-TCNQ molecules preferentially accumulated near the silicon surface.

Semiconductor‐Based Photoelectrochemical Water Splitting at the Limit of Very Wide Depletion Region

In semiconductor‐based photoelectrochemical (PEC) water splitting, carrier separation and delivery largely relies on the depletion region formed at the semiconductor/water interface. As a Schottky junction device, the trade‐off between photon collection and minority carrier delivery remains a persistent obstacle for maximizing the performance of a water splitting photoelectrode. Here, it is demonstrated that the PEC water splitting efficiency for an n‐SrTiO3 (n‐STO) photoanode is improved very significantly despite its weak indirect band gap optical absorption (α < 104 cm−1), by widening the depletion region through engineering its doping density and profile. Graded doped n‐SrTiO3 photoanodes are fabricated with their bulk heavily doped with oxygen vacancies but their surface lightly doped over a tunable depth of a few hundred nanometers, through a simple low temperature reoxidation technique. The graded doping profile widens the depletion region to over 500 nm, thus leading to very efficient charge carrier separation and high quantum efficiency (>70%) for the weak indirect transition. This simultaneous optimization of the light absorption, minority carrier (hole) delivery, and majority carrier (electron) transport by means of a graded doping architecture may be useful for other indirect band gap photocatalysts that suffer from a similar problem of weak optical absorption.

I-V CHARACTERISTICS AND TRANSCONDUCTANCE MODELING FOR DUAL CHANNEL ALGAN/GAN MODFETS

In this paper we present 2-D analytical model for I-V characteristics and transconductance of dual channel AlGaN/GaN Modulation Doped Field Effect Transistor (DC-MODFET) to demonstrate the current-voltage as well as transfer characteristics of the device structure under different bias conditions. The model analyses sheet charge density and finaly current density in each of the top and bottom channels using effective device threshold expressions based on spontaneous and piezoelectric polarization dependent two dimensional electron gas (2-DEG). An aluminum mole fraction graded doping profile in bottom barrier layer has been used for bottom channel sheet carrier density. Trapping/detrapping surface states are also considered to determine device drive current and trans-conductance expressions. The presence of double channels in the device minimize the current collapse problems, is accurately explained in our proposed model. The current collapse that occurs more in the top channel nearer to the gate, is subsidized by the current in bottom channel, hence minimizing overall current collapse in the device. Finally, the numerical predictions from our model are compared with the published experimental results and found to be in close agreement.

Enhanced Seebeck coefficient of bismuth telluride compounds with graded doping profiles

Thermoelectric properties of Bi-Sb-Te and Bi-Se-Te compounds with graded Ag doping profiles are reported. A junction structure with graded doping is formed in the Bi-Te based compounds through thermally driven Ag diffusion, which has demonstrated a greatly enhanced Seebeck coefficient when a thermal gradient is applied in the same direction of carrier concentration gradient. A mechanism based on the spatial variation of bandgap narrowing induced by heavy-doping effect is proposed to explain the anomalous thermoelectric property of Bi-Te based compounds with graded doping profiles.

비균일 100V 급 초접합 트랜치 MOSFET 최적화 설계 연구

전력 MOSFET(산화물-반도체 전위 효과 트랜지스터)는 BLDC 모터와 전력 모듈 등에 광범위하게 사용하고 있다. 기존 전력 MOSFET 구조는 온-저항과 항복전압사이에 절충(tradeoff)이 필요하다. 이러한 절충을 하지 않고 최적화를 하기위해 비균일 초접합 트랜치 MOSFET 를 설계하는데 동일한 항복전압에서 균일 초접합 트랜치 MOSFET보다 낮은 온-저항을 갖도록한다. 이를 위해 드리프트 영역에서 우수한 전기장 분포를 달성하기 위하여 선형구조의 도핑 프로파일을 제안하고, 단위 셀 설계, 도핑농도의 특성분석, 전위분포를 SILVACO TCAD 2D인 Atlas 소자 소프트웨어를 사용하여 시뮬에이션을 수행하였다. 결과로 100V 급 MOSFET에서 비균일 초접합 트랜치 MOSFET가 균일 초접합 트랜치 MOSFET보다 온-저항에서 우수한 특성을 보여주고 있다.

Preparation of 100 GHz InP Transferred Electron Devices

This paper reports on the development of InP transferred-electron-device sources in mainland of China for operation at around 100 GHz. Using n+-n-n+ structure with graded doping profiles, the oscillations were obtained at 101.8 GHz from a 1 μm structure with an n-doped drift zone and the doping concentration linearly increases from 1.0×1016 to 3.0×1016cm-3. Its continuous wave radio frequency (CWRF) output power was evaluated to be several milliwatt and these results are believed to correspond to a fundamental mode operation. This result is attributed to a processing technique based on the use of etch-stop layers, removal of substrate and the formation of good ohmic contacts.

Single-heterostructure laser diode producing a <inline-formula><math display="inline" overflow="scroll"><mrow><mn mathvariant="bold">6</mn><mrow><mtext> </mtext><mtext> </mtext><mi mathvariant="normal">W</mi></mrow><mo>/</mo><mn mathvariant="bold">40</mn><mtext> </mtext><mtext> </mtext><mi>ps</mi></mrow></math></inline-formula> optical pulse from a <inline-formula><math display="inline" overflow="scroll"><mrow><mn mathvariant="bold">20</mn><mrow><mtext> </mtext><mo>μ</mo><mi mathvariant="bold">m</mi></mrow></mrow></math></inline-formula> stripe width

A compact, low-cost semiconductor laser diode producing 40 ps full width at half maximum (FWHM) single-spike lasing pulses with 6 Watts peak power from a 20 μm stripe width is realized in the form of a simple single-heterostructure, grown by metal-organic chemical vapor deposition. The structure possesses a linearly graded doping profile extending from the p+ and n+ sides towards the p-n junction. This laser diode is operated under room temperature conditions and applies pumping current pulses (roughly 10 to 20 A/2 to 3 ns FWHM) achievable with a commercially available silicon avalanche transistor as an electrical switch.

Realization of 850V breakdown voltage LDMOS on Simbond SOI

In this paper, 850V breakdown voltage LDMOS fabricated on Simbond SOI wafer are reported. Simbond SOI wafers with 1.5@mm top silicon, 3@mm buried oxide layer, and n-type heavy doped handle wafers are used. In order to achieve uniform lateral electric field and shorten the vertical impact ionization integration path simultaneously, an optimized 60@mm drift region implant mask is designed to realize a linearly graded doping profile, and silicon thickness in the drift region is reduced from 1.5@mm to about 0.26@mm by thick field oxide process. CMOS compatible SOI LDMOS processes are designed and implemented successfully. Off-state breakdown voltage of SOI LDMOS can reach 850V, and the specific on-resistance is 56@Wmm^2. Experimental results also show the thickness of the top silicon in the drift region has a good uniformity. The performance of SOI LDMOS indicated that Simbond SOI wafers are good choice for thin film high voltage devices.

Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation

A novel graded doping profile, for the first time is introduced for reliability improvement and leakage current reduction. The proposed structure is called graded doping channel SiGe-on-insulator (GDC-SGOI). The key idea in this work is to modify the electric field and band energy with novel doping distribution in the channel for improving leakage current and hot electron. Using two-dimensional two-carrier simulation we demonstrate that the GDC-SGOI shows lower electron temperature near the drain region in the channel in comparison with the conventional SGOI (C-SGOI) with uniform doping. On the other hand, short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement leads to leakage current reduction. DIBL decrement and less dependence of the threshold voltage and DIBL on channel length variation in the GDC-SGOI structure show SCEs suppression. Furthermore the on–off current ratio ( I on/ I off) in the GDC-SGOI is higher than that achieved from the C-SGOI. Therefore, the results show that the GDC-SGOI structure especially in low power and device reliability has excellent performance in comparison with the C-SGOI.

Optimizing GaN photocathode structure for higher quantum efficiency

To improve the quantum efficiency of GaN photocathode, we optimized the photocathode's structure in three aspects. We use AlN replacing GaN as the buffer layer, which can act as potential barrier to reflect electrons back to surface. The optimal thickness of emission layer is calculated as 162.5nm, and considering the graded doping profile, we optimized the thickness as 180nm. Three built-in electric fields are introduced by Mg graded dope, and the intensities of the high fields are calculated to give the quantitive results of their influence. After surface cleaning and activation, quantum efficiency of the optimized sample was increased and the highest value of 56% was achieved at 240nm. More quantum efficiency enhancement is possible by further optimizing the photocathode structure.

High Quantum Efficiency Dependence on Structure Optimizatin for Gallium Nitride Photocathode

We optimized the gallium nitride(GaN)photocathode’s structure in three aspects for higher quantum efficiency. AlN is used to replace GaN as the buffer layer, which can act as potential barrier to reflect electrons back to surface. The optimal thickness of emission layer is calculated as 162.5nm, and considering the graded doping profile, we optimized the thickness as 180nm. Three built-in electric fields are introduced by Mg graded doping, and the intensities of the high fields are calculated to give the quantitive results of their influence on quantum efficiency. After surface cleaning and activation, quantum efficiency of the optimized sample was greatly increased and the highest value of 56% was achieved at 5.20eV. More quantum efficiency enchancement is possible by further optimizing the photocathode structure.

Hybrid Si Nanowire/Amorphous Silicon FETs for Large-Area Image Sensor Arrays

Silicon nanowire (SiNW) field-effect transistors (FETs) were fabricated from nanowire mats mechanically transferred from a donor growth wafer. Top- and bottom-gate FET structures were fabricated using a doped a-Si:H thin film as the source/drain (s/d) contact. With a graded doping profile for the a-Si:H s/d contacts, the off-current for the hybrid nanowire/thin-film devices was found to decrease by 3 orders of magnitude. Devices with the graded contacts had on/off ratios of ∼10(5), field-effect mobility of ∼50 cm(2)/(V s), and subthreshold swing of 2.5 V/decade. A 2 in. diagonal 160 × 180 pixel image sensor array was fabricated by integrating the SiNW backplane with an a-Si:H p-i-n photodiode.

Surface leakage current reduction in long wavelength infrared type-II InAs/GaSb superlattice photodiodes

Dielectric passivation of long wavelength infrared type-II InAs/GaSb superlattice photodetectors with different active region doping profiles has been studied. SiO2 passivation was shown to be efficient as long as it was not put in direct contact with the highly doped superlattice. A hybrid graded doping profile combined with the shallow etch technique reduced the surface leakage current in SiO2 passivated devices by up to two orders of magnitude compared to the usual design. As a result, at 77 K the SiO2 passivated devices with 10.5 μm cutoff wavelength exhibit an R0A of 120 Ω cm2, RmaxA of 6000 Ω cm2, and a dark current level of 3.5×10−5 A cm−2 at −50 mV bias.