Chiplets and heterogeneous integration are now common vernacular in the semiconductor industry. One of the more pressing issues facing device designers and system architects in this new reality is the insatiable appetite for high-bandwidth memory tightly integrated with GPU, CPU and other chiplet processing devices. This ever-increasing drive for higher levels of integration is resulting in module sizes that now exceed the bounds of the industry’s current de-facto standard silicon interposer solutions. With module dimensions exceeding 50 mm on a side, the industry is transitioning to organic substrates or molded fan-out interposers with embedded bridge die. These embedded bridge technologies provide a practical roadmap for significant module size growth to 100mm per side and beyond. As module sizes continue to grow, the number of embedded bridge die similarly increase. An emerging device currently in design now exceeds 20 bridge die. During assembly of the molded interposer, manufacturing tolerances to achieve the true positions required for all the bridge die become incredibly challenging to achieve in a cost-effective high-volume process. Within this paper, an innovative solution, Adaptive Pad Stacks, will be presented which increases process tolerances by up to 10X versus the conventional approach. For example, the ± 1.5 µm true position required for 35 µm pitch bridge die interfaces can be achieved with a die attach specification allowing up to ± 25 µm. Adaptive Pad Stacks utilize Adaptive Patterning® and mask-less laser direct imaging photolithography to not only deliver high yield on large scale interposers, but also remove the historical challenge with reticle stitching.
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