GPU Devices Research Articles

Performance Limits Study of Stencil Codes on Modern GPGPUs

We study the performance limits of different algorithmic approaches to the implementation of a sample problem of wave equation solution with a cross stencil scheme. With this, we aim to find the highest limit of the achievable performance efficiency for stencil computing. To estimate the limits, we use a quantitative Roofline model to make a thorough analysis of the performance bottlenecks and develop the model further to account for the latency of different levels of GPU memory. These estimates provide an incentive to use spatial and temporal blocking algorithms. Thus, we study stepwise, domain decomposition, and domain decomposition with halo algorithms in that order. The knowledge of the limit incites the motivation to optimize the implementation. This led to the analysis of the block synchronization methods in CUDA, which is also provided in the text. After all optimizations, we have achieved 90% of the peak performance, which amounts to more than 1 trillion cell updates per second on one consumer level GPU device.

A Novel Memory-Scheduling Strategy for Large Convolutional Neural Network on Memory-Limited Devices.

Recently, machine learning, especially deep learning, has been a core algorithm to be widely used in many fields such as natural language processing, speech recognition, object recognition, and so on. At the same time, another trend is that more and more applications are moved to wearable and mobile devices. However, traditional deep learning methods such as convolutional neural network (CNN) and its variants consume a lot of memory resources. In this case, these powerful deep learning methods are difficult to apply on mobile memory-limited platforms. In order to solve this problem, we present a novel memory-management strategy called mmCNN in this paper. With the help of this method, we can easily deploy a trained large-size CNN on any memory size platform such as GPU, FPGA, or memory-limited mobile devices. In our experiments, we run a feed-forward CNN process in some extremely small memory sizes (as low as 5 MB) on a GPU platform. The result shows that our method saves more than 98% memory compared to a traditional CNN algorithm and further saves more than 90% compared to the state-of-the-art related work “vDNNs” (virtualized deep neural networks). Our work in this paper improves the computing scalability of lightweight applications and breaks the memory bottleneck of using deep learning method on memory-limited devices.

Key Enabling Materials for 3DIC Fabrication and Device Performance

As the electronics industry reaches the limits of lithographic processing at sub-10nm dimensions, alternate approaches to meet the demand for increasing device density, reducing package size and improving device performance are being explored. Die stacking approaches to reduce the path length between CPU, GPU and memory devices using a heterogeneous 3DIC chip stacking technology have recently been announced, while memory manufacturers have been creating HBM die stacks for use in servers and highspeed applications. At DuPont Electronics & Imaging (E&I), we have been working to enable 3DIC technology through the development of chemicals and processes such as CMP pads and slurries for polishing all the critical materials, chemical cleaners to remove residues, and photoresists to pattern TSVs, pads and pillars. In addition to these materials, E&I also provides permanent materials for hybrid bonding, including electrodeposited copper for TSVs, pads and pillars as well as tin-silver for pillar capping. Another critical part of hybrid bonding is the adhesive bonding material, which needs to be planarized and yet still have sufficient flow to bond at the same time as the Cu-Cu or Cu-SnAg interconnect. This paper will demonstrate how these critical materials can be used together to fabricate 3DIC devices using a conventional bonding tool. Processing of wafers with sub-20 micron pillars has been completed with good metal joining and void-free bonding of the BCB-based polymer adhesive.

PPT-GPU: Scalable GPU Performance Modeling

Performance modeling is a challenging problem due to the complexities of hardware architectures. In this paper, we present PPT-GPU, a scalable and accurate simulation framework that enables GPU code developers and architects to predict the performance of applications in a fast, and accurate manner on different GPU architectures. PPT-GPU is part of the open source project, Performance Prediction Toolkit (PPT) developed at the Los Alamos National Laboratory. We extend the old GPU model in PPT that predict the runtimes of computational physics codes to offer better prediction accuracy, for which, we add models for different memory hierarchies found in GPUs and latencies for different instructions. To further show the utility of PPT-GPU, we compare our model against real GPU device(s) and the widely used cycle-accurate simulator, GPGPU-Sim using different workloads from RODINIA and Parboil benchmarks. The results indicate that the predicted performance of PPT-GPU is within a 10 percent error compared to the real device(s). In addition, PPT-GPU is highly scalable, where it is up to 450x faster than GPGPU-Sim with more accurate results.

Fast Analytic Simulation for Multi-Laser Heating of Sheet Metal in GPU.

Interactive multi-beam laser machining simulation is crucial in the context of tool path planning and optimization of laser machining parameters. Current simulation approaches for heat transfer analysis (1) rely on numerical Finite Element methods (or any of its variants), non-suitable for interactive applications; and (2) require the multiple laser beams to be completely synchronized in trajectories, parameters and time frames. To overcome this limitation, this manuscript presents an algorithm for interactive simulation of the transient temperature field on the sheet metal. Contrary to standard numerical methods, our algorithm is based on an analytic solution in the frequency domain, allowing arbitrary time/space discretizations without loss of precision and non-monotonic retrieval of the temperature history. In addition, the method allows complete asynchronous laser beams with independent trajectories, parameters and time frames. Our implementation in a GPU device allows simulations at interactive rates even for a large amount of simultaneous laser beams. The presented method is already integrated into an interactive simulation environment for sheet cutting. Ongoing work addresses thermal stress coupling and laser ablation.

Fine line panel level fan out changes the SiP landscape

Abstract Moore's Law has been through many challenges in the last few years. The transistors continued to shrink to smaller sizes but the benefit of better performance and lower cost that comes along with shrinking is facing difficulties. Semiconductor industries are trying to come up with new ways to keep the Moore's Law going on two different fronts: where foundries are working on more Moore solutions and packaging houses are working on more than Moore solutions. Recently the industry has been considering the chip splitting and re-constitution in the form of SiP which has relatively shorter development time and lower cost than the SoC. But traditional SiP with wirebonding or FC connections to substrate will lead to high transmission loss and power consumption. A new fine line SiP solution is required to shorten the connection between chips to improve the performance. Different from the 3DIC and 2.5DIC technologies, fine line panel level fan out has the advantages of good performance, design flexibility, and high production efficiency. This paper will discuss about the challenges in setting up this technology including establishing standards, tools preparation, and process difficulties. The dedicated machines that handle the fine line panel level fan out are critical. It is not easy to select suitable tools for this new technology. We also need to co-develop with tool vendors for some process stages which suitable tools from existing industries could not be easily found. Additionally, panel warpage and chip shift are two of major process challenges. Experiences on overcoming these difficulties will be shared. Different structures and processes have been developed for varied application requirements. The chip first approach encapsulates chips and then build RDL layers on the encapsulation surface. It is suitable for mobile AP, baseband, ASIC, PMIC, and memory. The chip last solution build RDL first, then flip chip mounting the bumped chips on the RDL. The RDL can be tested before the mounting of chips. It is suitable for CPU, GPU, FPGA, and thermal sensitive devices. Pillars in fan out is a chip middle solution. It uses Cu pillars to connect top and bottom RDLs which is good for chip stacking. Currently the 5/5um line/space is already been qualified. 3/3um under development and tool capability is 2/2um. Several real cases will be demonstrated in this paper to help the readers understand this technology. This technology is expected to be crucial for the coming era of 5G, automotive, IoT, and AI. It is believed that this technology can be applied to different kinds of end applications. For example, multi-chip stacking in a fan out package to achieve high bandwidth performance. Fan out stacking of logic and memory chips which can replace the existing PoP. Using fan out to integrate passives and/or other chips can achieve a compact SiP. Fan out could be one of the embedded substrate. Fan out RDL process can also be a suitable platform for antenna in package designs. This paper will introduce the challenges of Moore's law as beginning, and then explain the advantages and the challenges of fine line panel fan out technology, and the proposed approaches to address those challenges.

Performance of a Second Order Electrostatic Particle-in-Cell Algorithm on Modern Many-Core Architectures

In this paper we present the outline of a novel electrostatic, second order Particle-in-Cell (PIC) algorithm, that makes use of 'ghost particles' located around true particle positions in order to represent a charge distribution. We implement our algorithm within EMPIRE-PIC, a PIC code developed at Sandia National Laboratories. We test the performance of our algorithm on a variety of many-core architectures including NVIDIA GPUs, conventional CPUs, and Intel's Knights Landing. Our preliminary results show the viability of second order methods for PIC applications on these architectures when compared to previous generations of many-core hardware. Specifically, we see an order of magnitude improvement in performance for second order methods between the Tesla K20 and Tesla P100 GPU devices, despite only a 4× improvement in the theoretical peak performance between the devices. Although these initial results show a large increase in runtime over first order methods, we hope to be able to show improved scaling behaviour and increased simulation accuracy in the future.

Supercomputer Simulations in Design of Ultrasound Tomography Devices

The paper considers the use of supercomputers in design of medical ultrasound tomography devices. The mathematical models describing the wave propagation in ultrasound tomography should take into account such physical phenomena as diffraction, multiple scattering, and so on. The inverse problem of wave tomography is posed as a coefficient inverse problem with respect to the wave propagation velocity and the absorption factor. Numerous simulations made it possible to determine the optimal parameters of an ultrasound tomograph in order to obtain a spatial resolution of 1.5 mm suitable for early-stage breast cancer diagnosis. The developed methods were tested both on model problems and on real data obtained at the experimental test bench for tomographic studies. The computations were performed on GPU devices of Lomonosov-2 supercomputer at Lomonosov Moscow State University.

An adaptive algorithm for high‐dimensional integrals on heterogeneous CPU‐GPU systems

SummaryIn this paper, we introduce an adaptive procedure for the numerical computation of a high‐dimensional integrals on HPC systems with heterogeneous nodes composed of multi‐core CPU and GPU devices. To this aim, we have integrated together two different approaches: a first one is in charge of a fair workload among the threads running on the multi‐core CPU, while a second one is in charge of an efficient execution of the computational kernels on the GPU. We tested the resulting algorithm on several test functions on a system where the nodes are provided with two Intel ten‐core CPU and one NVIDIA GPU device.

Controlling Complexity of Cerebral Cortex Simulations-I: CxSystem, a Flexible Cortical Simulation Framework.

Simulation of the cerebral cortex requires a combination of extensive domain-specific knowledge and efficient software. However, when the complexity of the biological system is combined with that of the software, the likelihood of coding errors increases, which slows model adjustments. Moreover, few life scientists are familiar with software engineering and would benefit from simplicity in form of a high-level abstraction of the biological model. Our primary aim was to build a scalable cortical simulation framework for personal computers. We isolated an adjustable part of the domain-specific knowledge from the software. Next, we designed a framework that reads the model parameters from comma-separated value files and creates the necessary code for Brian2 model simulation. This separation allows rapid exploration of complex cortical circuits while decreasing the likelihood of coding errors and automatically using efficient hardware devices. Next, we tested the system on a simplified version of the neocortical microcircuit proposed by Markram and colleagues ( 2015 ). Our results indicate that the framework can efficiently perform simulations using Python, C , and GPU devices. The most efficient device varied with computer hardware and the duration and scale of the simulated system. The speed of Brian2 was retained despite an overlying layer of software. However, the Python and C devices inherited the single core limitation of Brian2. The CxSystem framework supports exploration of complex models on personal computers and thus has the potential to facilitate research on cortical networks and systems.

Accelerating the K-Nearest Neighbors Filtering Algorithm to Optimize the Real-Time Classification of Human Brain Tumor in Hyperspectral Images.

The use of hyperspectral imaging (HSI) in the medical field is an emerging approach to assist physicians in diagnostic or surgical guidance tasks. However, HSI data processing involves very high computational requirements due to the huge amount of information captured by the sensors. One of the stages with higher computational load is the K-Nearest Neighbors (KNN) filtering algorithm. The main goal of this study is to optimize and parallelize the KNN algorithm by exploiting the GPU technology to obtain real-time processing during brain cancer surgical procedures. This parallel version of the KNN performs the neighbor filtering of a classification map (obtained from a supervised classifier), evaluating the different classes simultaneously. The undertaken optimizations and the computational capabilities of the GPU device throw a speedup up to 66.18× when compared to a sequential implementation.

GMMA: GPU-based multiobjective memetic algorithms for vehicle routing problem with route balancing

A multiobjective optimization problem called a vehicle routing problem with route balancing (VRPRB) is studied. VRPRB extends traditional VRPs by considering two objectives simultaneously. The first objective is the minimization of the total traveling cost and the second one tries to ensure the balance among multiple routes. Different from another commonly used balancing objective, namely, the minimization of the difference between the maximal and minimal route cost, the objective we introduce is the minimization of the maximal route cost. Such setting can effectively avoid the occurrence of distorted solutions. In order to find Pareto-optimal solutions of VRPRB, we develop a multiobjective memetic algorithm (MMA), which integrates a problem-specific local search procedure into a multiobjective evolutionary algorithm. The MMA is further enhanced by using parallel computations on GPU devices. A simple version and a revised version of GPU-based MMAs are proposed and implemented on the CUDA platform. All the algorithms are tested on the benchmark instances to demonstrate their efficacy and effectiveness. Furthermore, the performances of CPU-based and GPU-based algorithms are analyzed.

Parallel SIMD CPU and GPU Implementations of Berlekamp–Massey Algorithm and Its Error Correction Application

The Berlekamp–Massey algorithm finds the shortest linear feedback shift register for a binary input sequence. A wide range of applications like cryptography and digital signal processing use this algorithm. This research proposes novel parallel mechanisms offered by heterogeneous CPU and GPU hardwares in order to achieve the best possible performance for BMA. The proposed bitwise implementation of the BMA algorithm is almost 35 times faster than state of the art implementations. This further improvement is achieved by using SIMD instructions which provides data level parallelism. This new approach can be 4.6 and 35 times faster than a bitwise CPU and state of the art implementations, respectively. In order to achieve the highest possible speedup over a multi-core structure, a multi-threading implementation is introduced in this research. By leveraging on OpenMP we were able to obtain a speedup of 10 times over 12 cores server. The GPU device with thousands of processing cores can bring great speedup over the best CPU implementation. Two other parallel mechanisms offered by GPU are concurrent kernel execution and streaming. They achieve 14.5 and 2.2 times of speedup compared to CPU serial and typical CUDA implementations, respectively. Also, the performance of the openMP code with SIMD instructions is compared with GPU stream implementation. The effectiveness of the proposed method is evaluated in a real world error correction application and it achieves 6.8 times of speedup.

Real-time biscuit tile image segmentation method based on edge detection

In this paper we propose a novel real-time Biscuit Tile Segmentation (BTS) method for images from ceramic tile production line. BTS method is based on signal change detection and contour tracing with a main goal of separating tile pixels from background in images captured on the production line. Usually, human operators are visually inspecting and classifying produced ceramic tiles. Computer vision and image processing techniques can automate visual inspection process if they fulfill real-time requirements. Important step in this process is a real-time tile pixels segmentation. BTS method is implemented for parallel execution on a GPU device to satisfy the real-time constraints of tile production line. BTS method outperforms 2D threshold-based methods, 1D edge detection methods and contour-based methods. Proposed BTS method is in use in the biscuit tile production line.

Parallelization of the numerical simulation of motion of deformable objects within fluid domain on a GPU device

Computationally demanding numerical simulations can be significantly accelerated using GPU (Graphics Processing Unit) devices. This way, the results of the simulation can be observed in real time. In this paper, the principles of GPU programming are used to simulate the movement of deformable objects within fluid domain. Lattice Boltzmann (LB) method is used to simulate fluid flow. The solid-fluid interaction is modeled using the Immersed boundary method. The developed software was tested on a Tesla GPU device; the execution time of parallelized version and sequential version of the software are compared and significant speed-up is obtained. Fluid flow simulations in the field of biomedicine that needed up to several hours to be performed, can now be completed in just a few minutes.

Improving the energy efficiency of SMACOF for multidimensional scaling on modern architectures

The reduction of the dimensionality is of great interest in the context of big data processing. Multidimensional scaling methods (MDS) are techniques for dimensionality reduction, where data from a high-dimensional space are mapped into a lower-dimensional space. Such methods consume relevant computational resources; therefore, intensive research has been developed to accelerate them. In this work, two efficient parallel versions of the well-known and precise SMACOF algorithm to solve MDS problems have been developed and evaluated on multicore and GPU. To help the user of SMACOF, we provide these parallel versions and a complementary Python code based on a heuristic approach to explore the optimal configuration of the parallel SMACOF algorithm on the available platforms in terms of energy efficiency (GFLOPs/watt). Three platforms, 64 and 12 CPU-cores and a GPU device, have been considered for the experimental evaluation.

Fast, energy-efficient electronic structure simulations for multi-million atomic systems with GPU devices

We report that speed and energy efficiency of large-scale electronic structure simulations, which target realistically sized systems consisting of multi-million atoms, can be hugely improved with o...

How to exploit high performance computing in population-based metaheuristics for solving association rule mining problem

The application of population-based metaheuristics approaches to the association rules mining problem is explored in this paper. The combination of GPU and cluster-based parallel computing techniques is investigated for the purpose of accelerating the process of extracting the correlations between items in sizeable data instances. We propose four parallel-based approaches that benefit from the cluster intensive computing in the generation process and the massively GPU threading. This is by evaluating the association rules in parallel on GPU. To validate the proposed approaches, the most used population-based metaheuristics (GA, PSO, and BSO) have been executed on a cluster of GPUs to solve benchmarks of large and big ARM instances. We used Intel Xeon 64bit quad-core processor E5520 coupled to an Nvidia Tesla C2075 GPU device. The results show that the BSO outperforms GA and PSO. They also show that the proposed solution outperforms the HPC-based ARM approaches when exploring Webdocs instance (the largest instance existing on the web). To our knowledge, this is the first work that explores the combination of GPU and cluster-based parallel computing with the population-based metaheuristics in association rule mining.

HetSpark: A Framework that Provides Heterogeneous Executors to Apache Spark

The increasing computational complexity of Big Data software requires the scale up of the nodes of clusters of commodity hardware that have been used widely for Big Data workloads. Thus, FPGA-based accelerators and GPU devices have recently become a first class citizen in data centers. Utilizing these devices is not trivial task however from an engineering effort perspective since developers versed in distributed computing frameworks, such as Apache Spark are used to developing in higher level languages and APIs, like Python and Scala, while accelerators require the use of low-level APIs like Cuda and OpenCl.Through recent developments in accelerator virtualization like VineTalk [6] a software layer that handles the complex communication between applications and FPGAs or GPU devices, software development using accelerators has been simplified.This paper presents HetSpark, a heterogeneous modification of Apache Spark. HetSpark enables Apache Spark to operate with two classes of executors: an accelerated class, and a commodity class. HetSpark applications are expected to use VineTalk for their entire interaction with accelerators. The schedulers of HetSpark are sophisticated enough to detect the existence of VineTalk routines in the java binary code. Thus, they take decisions as to which tasks require the use of accelerators, and they send them only to executors of the former class.Finally, we evaluated thoroughly the performance of HetSpark with different mixes of executors of the two different classes. When applications run linear tasks, we observed that the use of CPU-only accelerators is preferable to GPU enhanced accelerators, while for applications with computationally challenging tasks, the time savings from the use of GPUs compensate for data transfers between commodity and accelerated executors.

Toward Exascale Computing Systems: An Energy Efficient Massive Parallel Computational Model

The emerging Exascale supercomputing system expected till 2020 will unravel many scientific mysteries. This extreme computing system will achieve a thousand-fold increase in computing power compared to the current petascale computing system. The forthcoming system will assist system designers and development communities in navigating from traditional homogeneous to the heterogeneous systems that will be incorporated into powerful accelerated GPU devices beside traditional CPUs. For achieving ExaFlops (10^18 calculations per second) performance through the ultrascale and energy-efficient system, the current technologies are facing several challenges. Massive parallelism is one of these challenges, which requires a novel energy-efficient parallel programming (PP) model for providing the massively parallel performance. In the current study, a new parallel programming model has been proposed, which is capable of achieving massively parallel performance through coarse-grained and fine-grained parallelism over inter-node and intra-node architectural-based processing. The suggested model is a tri-level hybrid of MPI, OpenMP and CUDA that is computable over a heterogeneous system with the collaboration of traditional CPUs and energy-efficient GPU devices. Furthermore, the developed model has been demonstrated by implementing dense matrix multiplication (DMM). The proposed model is considered an initial and leading model for obtaining massively parallel performance in an Exascale computing system.