Good Control Of Short Channel Effects Research Articles

Impact of PVT Variations on Optimizing Silicon Power

The scaling of CMOS technology faces challenges as the demand rises, but FinFETs emerging as a vital alternative for 22nm technology node and lower. Otherwise, FinFETs tend to have multiple PVT variations, making static timing analysis (STA) more flexible and suitable to analyze the timing delay of the logic generation. Device simulation and statistical temporal analysis are used to derive PVT variation models for FinFET-based standard cell designs. Mixing different FinFET design styles shows promise in optimizing delays and leakage, as FinFETs offer better control of short-channel effects and processing scalability. Furthermore, lowering clock skew is also a prime design aspect to consider. However, as technology scales to smaller devices, process, voltage, and temperature (PVT) variations make minimizing clock distortion very difficult. To mitigate the effects of PVT variations, many previous works proposed a Post Silicon Tuning (PST) architecture to dynamically balance the skew of the clock tree. In this paper, we will disclose the details of clock tree synthesis optimizations and FinFET logic developments minimizing PVT variations.

Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process

The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.

Threshold Voltage Variability in Nanosheet GAA Transistors

Nanosheet gate-all-around (GAA) field-effect transistor (NSFET) is a potential replacement for the FinFET at advanced technology nodes owing to better control of short-channel effects and higher drive current. Due to the increased complexity of the GAA stacked structure, new forms of process variability come into the picture, which are dominant over the conventional process variability such as metal gate granularity (MGG) and line edge roughness (LER) for FinFETs. In this article, we show one such process variability called as metal thickness variation (MTV). MTV causes WF variations on the gates of the GAA sheet transistor and results in a significant VT variability. The impact of MTV is studied using an analytical framework. We studied three variants of NSFETs and reported variability in terms of key device design parameters such as intersheet spacing and metal thicknesses. The results presented here help in designing the process flow for a type of NSFET to minimize the VT variability.

CMOS-Compatible Replacement Metal Gate InGaAs-OI FinFET With $I_{ON}=156~\mu \text{A}/\mu \text{m}$ at $V_{DD}= 0.5$ V and $I_{OFF}=100$ nA/$\mu \text{m}$

We report CMOS-compatible $n$ -channel InGaAs-on-insulator FinFETs obtained using a replacement metal gate fabrication flow. The fabricated devices feature 12-nm-thick SiNx spacers, a scaled high- $k$ /metal gate (capacitance equivalent thickness of $\sim 1.5$ nm), raised source and drain doped to $\sim 6\times 10^{19}$ /cm3, and fin width scaled down to 15 nm. Very good control of short-channel effects is demonstrated down to a gate length of 50 nm with a minimum subthreshold swing of 92 mV/decade at $V_{DS}=0.5$ V and a drain-induced barrier lowering of 57 mV/V. An ON-state current ( $I_{{\textit {ON}}})$ of 156 $\mu \text{A}/\mu \text{m}$ is also reported for a supply voltage of 0.5 V and a fixed OFF-state current of 100 nA/ $\mu \text{m}$ . This $I_{ON}$ value is the highest reported to date for CMOS-compatible InGaAs devices integrated on Si.

High-Frequency Performance of Trigate Poly-Si Thin-Film Transistors by Microwave Annealing

This letter investigates the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) using low temperature microwave annealing (MWA). MWA exhibits sufficient dopant activation efficiency, good short channel effect control, and a higher maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of poly-Si TFTs than does rapid thermal annealing. In addition, MWA can fabricate nanoscale devices. Poly-Si TFTs with short channel annealed by microwave reveals better high-frequency performance and switching characteristics.

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Continued scaling of bulk CMOS technology is facing formidable challenges. FinFETs, with better control of short-channel effects, offer a promising alternative for the 22-nm technology node and beyond. However, FinFETs still suffer from process, voltage, and temperature (PVT) variations. Thus, to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis. In this paper, using an existing SSTA algorithm as a foundation, we analyze silicon-on-insulator FinFET circuits in various new ways: basing the analysis on accurate device simulation of the logic library; considering voltage and temperature variations, in addition to process variations; deriving accurate timing and leakage macromodels; and investigating the impact of PVT variations on delay/leakage distributions at the circuit level. We propose a simplified timing model that greatly reduces the computational complexity without giving rise to any convergence issues. The timing model has an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared with accurate quasi-Monte Carlo simulations. We evaluate the performance of our SSTA algorithm with respect to Monte Carlo simulation, and extend the algorithm to enable statistical leakage and dynamic power analysis as well. We investigate the impact of PVT variations on delay/power distributions at the circuit level. We show that deterministic optimization methods can optimize both the mean and variance of circuit delay/power distributions, and even the ratio of standard deviation to mean in some cases. Finally, we show that FinFET circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.5 V, good short-channel effect control, and high transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> =1.2 mS/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-1 V and 1.05 mS/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.5 V for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel

In this paper, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio and good short channel effect control on the channel potential. The current ratio is of ~6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> (ID) at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.1 V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> =-3, and 0 V. The relatively low OFF-current is of 6 nA/ μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.1 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> =0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =120 nm.

Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors

A comprehensive yet simple design methodology of silicon nanowire MOSFETs is presented. An analytical gate capacitance model for sub-22nm gate length is also proposed to gain insight into design optimization with quantum confinement included. In contrast to conventional bulk device design, this work shows that the wire diameter does not necessarily follow the common stringent scaling rule. An optimal device design window does exist while a moderate wire diameter dimension is suggested without the need of extremely scaled dimension. The nanowire diameter designed at two thirds of gate length minus three times gate oxide thickness is shown to achieve good control of short-channel effects.

Nanoscale FD/SOI CMOS: thick or thin BOX?

The question of buried-oxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses. Whereas, FD/SOI MOSFETs with thin BOX give better control of short-channel effects (SCEs), they complicate the material and/or process technologies and undermine CMOS speed. We show that the improved SCE control afforded by thin BOX is due to high transverse electric field in the body defined by the device asymmetry, and not only to the suppression of electric-field fringing in the BOX as is commonly presumed. Since conventional FD/SOI CMOS with thick BOX can be scaled via ultrathin bodies, we conclude that thin BOX is not needed nor desirable.

Scheme for the fabrication of ultrashort channel metal-oxide-semiconductor field-effect transistors

We present a scheme for the fabrication of ultrashort channel length metal-oxide-semiconductor field-effect transistors (MOSFETs) involving nanolithography and molecular-beam epitaxy. The active channel is undoped and is defined by a combination of nanometer-scale patterning and anisotropic etching of an n++ layer grown on a silicon on insulator wafer. The method is self-limiting and can produce MOSFET devices with channel lengths of less than 10 nm. Measurements on the first batch of n-MOSFET devices fabricated with this approach show very good output characteristics and good control of short-channel effects.