Gm-C Filter Research Articles

Pico-ampere resolution current measurement circuit using Gm-C filter sigma-delta modulator for low-power nanopore DNA sequencing

New generation DNA sequencers use an array of electrochemical cells equipped with nanopores, which produce pico-ampere current levels. Due to the large number of channels, low current levels and bandwidths in the order of a few kHz, in the design of these readout circuits, 2D arrays of in-channel, low noise and low power analog to digital converters are preferred. Previously many different sigma-delta modulators have been presented to convert the nanopore current signal into a digital code. Conventionally, the opamps required in these converters will eventually increase the power dissipation of each channel. In this paper a novel Gm-C filter based second order sigma-delta converter is proposed. In the given design, rather than relying on multiple opamps to achieve the necessary gain and noise performance, only a 4 transistor Gm block is used. Evaluations show that while the input referred noise remains close to previous methods, the power dissipation is considerably reduced. A prototype is also implemented to show the effectiveness of the approach. In a 180-nm design, an ENOB of 12.16 bits, RMS input referred noise of 0.2 pA at 10 kHz bandwidth and power dissipation of 8.27 μW is obtained per channel.

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.

Design and Characterization of a Digitally Tunable Gm-C Filter for Multi-Standard Receivers

This paper presents the design, simulation, prototyping, and measurement results of a digitally tunable fourth order Gm-C low-pass filter (LPF) for multi-standard radio receivers. The LPF cut-off frequency can be tunned by digitally selecting the transconductance of the basic reconfigurable operational transconductance amplifiers (OTAs) that compose the circuit. Four operation modes allow for control of the OTA transconductances and, consequently, the scaling of power consumption. The filter was designed and prototyped in a 1.8 V 180 nm CMOS process. The measurement results indicate that the configurability provides a cutoff frequency of 1.90/3.56/6.07/8.15 MHz with a power consumption ranging from 9.9 to 13.1 mW. The designed filter achieves an IIP3 of 8.17 dBm for a signal bandwidth of 8.15 MHz. The performance, in terms of power dissipation, noise, and cut-off frequency, is at the same order of magnitude compared to recent related works reported in the literature. The advantages are a compact area, small sensitivity to component mismatches, and low design complexity. The proposed filter presents electrical characteristics suitable for the application in radio receivers for multi-carrier WCDMA signals.

A Low-Power 30MHz ,6th Order Band-pass Differential Gm-C Filter on Chip Using Floating Current Source

A 30MHz center frequency, 6th order Butterworth and elliptic band-pass filter using a leap-frog Gm-C structure in this work. A continuous time differential voltage mode Gm-C biquad and its adjoin voltage - mode version are described, employing FCS (Floating Current Source) circuits as building blocks. The improved current source structure is simple and includes fewer transistors. This provides an effective use of the chip area and brings simplicity to the design of circuits. The proposed filter structure does not contain the resistor which is very important for integration. All capacitors in proposed filter are grounded which reduces the parasitic effects. The proposed filter has been successfully implemented by TSMC 0.18μm CMOS process. Simulation results are given to confirm the theoretical analysis.

Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL

High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([Formula: see text]-[Formula: see text])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [Formula: see text]-[Formula: see text] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [Formula: see text]-[Formula: see text] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [Formula: see text]3[Formula: see text]dB cut-off frequency of 16.51[Formula: see text]MHz and 17.22[Formula: see text]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[Formula: see text][Formula: see text]s and 0.32[Formula: see text][Formula: see text]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

Analog Signal Processing Using Current Mode Computational Circuits

In this study, enhanced linearity and wide linear range current adder and subtractor circuits based on cascode current mirrors are presented. Among other analogue signal processing devices, the described circuits can be employed in operational transconductance amplifiers (OTA), Gm-C filters, and amplifiers. To enhance current mirroring performance, the suggested circuits use the cascode current mirror topology. A 1.8-volt supply and TSMC 0.18-micron CMOS technology were used to model the suggested circuits. The suggested circuits have an allowed error percentage of less than 2.5% and perform well in the current range of 0 to 80 A. The outcomes of the SPICE simulation have shown how well the proposed circuits work.

A Configurable Interface for Analog Sensor Outputs

Reading out analog sensor outputs can be a challenging task at low frequencies because of the low frequency noise. To obtain a sensor signal clearly, special interface circuits are required. By using such circuits, analog signals are cleaned from offset, drift and 1/f noise. Besides, if the interface circuitry is configurable, it can be possible to interface to inputs at different frequency ranges. At the interface block, analog sensor output signal is moved to a frequency band where low frequency noise effects are not dominant by using chopping modulation technique. The frequency-shifted signal is then filtered using various filter types. To remove the low frequency noise before moving the signal back to the original band, Gm-C filter is used. The entire topology can be configured by a 5-bit digital to analog converter (DAC) called Biasing DAC (BDAC). This allows us to digitally change the biasing current of operational transconductance amplifiers (OTA), so that OTA based amplifiers and filters can operate at different frequency ranges. As conclusion, a configurable analog sensor interface has been designed. The design and layouts have been realized and simulated in Cadence Virtuoso using UMC 130nm CMOS technology.

Design metrics for operational tran conductance amplifier

It is a highly tough undertaking to build an analogue circuit, especially one that consumes little power [1-5]. A basic component in many analogue integrated circuits like ADC, Gm-C filter and Delta Sigma modulator is the Operational Transcondactance Amplifier commonly known as the OTA. In all of these integrated circuits, the structure of the OTA is of fundamental importance. Gain Bandwidth (GBW), DC Gain, Common Mode Rejection Ratio (CMRR) and average power are performance characteristics that decide the selection of the OTA [6]. A well-designed OTA that has outstanding processing attributes such as speed, power consumption, gain and GBW is an accomplishment in itself [15]. This chapter mainly examines the performance parameters theoretically as well as analytically, which determines the design of OTA. Optimization strategies which are applicable to low voltage and low power applications, notably at the level of the transistor are also examined.

A high-speed complementary current-mode Gm-C filter

A high-speed complementary current-mode Gm-C filter

Power Efficient Biquadratic Filter designing using OTA

Objectives: To present a power efficient Universal Biquad Operational Transconductance Amplifier circuit. Methods: OTA (operational transconductance amplifier) based Biquad filter is analyzed using three different simulated tools three different tools (CADENCE, XILINX, ORCAD and MATLAB tools) are used for designing the circuit. The 0.18mm CMOS technique is used using the Cadence tool for plan and reproduction. The same circuit has been implemented on ORCAD tool as well as Xilinx tool. Findings: The proposed Biquad filter improves the frequency response, power dissipation and provides vary of the KHN biquadratic filter circuits it uses minimum numbers of Operational Transconductance phenomenon Amplifier (OTA) to realize an equivalent. The assorted parameters specifically Center frequency, dcgain, Bandwidth, Power Dissipation and Quality issue are all electronically tunable. OTA based Biquad filter is simulated in CADENCE Virtuoso tool. Opamp-RC Biquad filter offers a bandwidth of 425 kHz, pass band gain of zero DB, whereas Gm-C measuring system based mostly filter offers 85MHz, passband gain of zero DB. Over-all power dissipation of the Biquad filter is 4.3mW with 1.8V DC Supply has basing current of 50mA with gracefully voltage 2.5v. by keeping the supply voltage, bias current and load capacitor as 2.5V, 50mA and 10pFrespectively, it has been seen that the power is reduced using the CADENCE virtuoso tool. Novelty : This study presents a Universal Biquadratic filter having less power dissipation. The circuit was optimized for gain, GBP, slew rate, areas, voltage offset, phase margin, power area etc. compared to all the previous filter circuits (OTA GMC filters, OTA type-C filters) designed with the help of OTA. Keywords: OTA; CMOS; CADENCE Virtuoso; Static Power; Dynamic Power; MOSFET

A 36.7 mW, 28 GHz receiver frontend using 40 nm RFCMOS technology with improved Figure of Merit

High carrier frequency requirement (Sub 6, 28 GHz) to accomplish the high bandwidth specification for millimeter wave band wireless communication, has reduced the ratio of operating carrier frequency (fc) and unity current gain frequency (ft) of MOSFETs in state of the art RFCMOS technology. This poses a challenge for designing a high gain and low noise receiver with better linearity. In an attempt to realize such receiver, this paper presents a 28 GHz receiver front-end in 40 nm RFCMOS technology. It includes 3-stage low noise amplifier incorporating push pull topology, current bleeding down converting gilbert cell based mixer with common gate transconductance stage followed by a standard Gm-C filter. By incorporating these techniques, the performance of the proposed receiver improved in terms of linearity as compared to the state of the art designs. For a comprehensive analysis, the combined effect of performance parameters has been compiled into a single metric i.e. Figure of Merit (FOM). The proposed receiver exhibits conversion gain of 30.5 dB and 2.15 dB noise figure with linearity parameter IIP3 being −21.7 dBm while consuming 36.7mW power resulting in FOM value of 0.27.

Design and simulation of fourth order low-pass Gm-C filter with novel auto-tuning circuit in 90 nm CMOS

A tunable high-frequency operational transconductance amplifier (OTA) is presented along with its application in the implementation of a Gm-C filter. The OTA is tuned by varying the negative resistance produced by a positive feedback at the output. Post-layout simulation results (using TSMC 90 nm CMOS technology and a 1-V supply voltage) show that the differential DC gain, common-mode gain and OTA unity gain frequency are 34 dB, −26 dB and 10 GHz, respectively. Moreover, for precise control of filter performance, an auto-tuning circuit is presented to adjust the filter cutoff frequency at low power consumption (i.e., 0.6 mW, about 16.3% of the total circuit power consumption). The filter has a cutoff frequency of 1 GHz with a group delay variation less than 6% up to 1.3 fc. The size of filter is 0.040 × 0.023mm2 and the third order intermodulation (IM3) value at cutoff frequency is −37 dB. The Monte Carlo simulation results are presented for predicting the manufacturing process errors.

NONLINEAR DISTORTION AND NOISE ANALYSIS OF GENERAL GM-C FILTERS

Systems such as Gm-C filters are ideally designed to exhibit linear characteristics. However, their components – especially transconductors – are intrinsically nonlinear. Although there exist many approaches that aim at reducing nonlinear effects while dealing with practical design problems, nonlinear distortion cannot be canceled out completely. Thus, it is important to estimate a degradation of filter performance caused by nonlinearities. In this paper we propose a simple and general method to perform a transient analysis of any Gm-C filter structure based on a matrix description and macro-modeling of transconductors. An analytical description of general Gm-C filters with nonlinear transconductors is introduced. A differential system that determines dynamics of a general structure of Gm-C filter is formulated. This allows us to carry out an effective and fast transient analysis of any Gm-C filter using standard numerical methods. The approach can be applied to investigate any non-linear effects in filters. The noise analysis of Gm-C filters in general setting is also presented. The accuracy of the proposed methods is confirmed by comparison with SPICE simulation. Example of application for performance optimization of 4th order Chebyshev filter is given.

Design of low power, programmable low-Gm OTAs and Gm-C filters for biomedical applications

In this paper, two programmable operational transconductance amplifiers (POTAs)—one using bulk driven attenuator (BDA) and another using programmable current mirror (PCM) are proposed in order to achieve low-Gm and high dynamic range. These OTAs are denoted as BDA-POTA and PCM-OTA respectively and are realized using composite transistors operated in the subthreshold region. The pseudo resistor is used for achieving programmability in the former and for improving the linearity and dynamic range in the latter. The proposed OTAs and two 4th order programmable Butterworth low pass filters (LPF) are designed and implemented in CMOS 180 nm technology with a supply voltage of 0.9 V. Their performances are evaluated through post-layout simulations and are found to be superior compared to those of POTAs reported in the literature for biomedical applications. The power consumption, transconductance, dynamic range and input-referred noise of BDA-POTA and PCM-OTA are [25.2 nW, (7.89–15.61 nS), (77.54–74.89 dB), (39.86–51.19 µVrms)] and [72.81 nW, (5.49–174.5 nS), (91.20–84.39 dB), (17.19–34.92 µVrms)] respectively. The power dissipation and cut off frequency range of the LPF using BDA-POTA and PCM-OTA are [197.8 nW, (30–100 Hz)] and [209.8 nW, (16–971 Hz)] respectively. The latter achieves 13.6 times wider programmability with only 5% increase in power dissipation. The proposed LPFs have better FOM compared to those reported in the literature.

An independent tuning current-reuse Gm-C complex biquad with high linearity

An independent tuning current-reuse Gm-C complex biquad is presented in this paper. By introducing extra freedoms, the proposed complex biquad achieves both independent tuning capability and higher linearity which are two big challenges preventing the reported current-reuse Gm-C filter from practical application. The prototype biquad is fabricated in standard 65-nm CMOS and the core circuit occupies 0.0512 mm2. It consumes 0.072 mW under 1.2-V supply. Monte Carlo (MC) simulation shows the proposed biquad features more robustness to mismatch variation. The center frequency and bandwidth of the biquad are about 2 MHz and 1.2 MHz, respectively. Measurement results indicate IIP3 of −9.53 dBm with image rejection ratio (IRR) of 25.3 dB.

Experimental silicon tunnel-FET device model applied to design a Gm-C filter

This work presents the design of a Gm-C filter using experimental data of a silicon tunneling field effect transistors (TFET) device. The application takes advantage of the low gm of a Si TFET device, resulting in an optimized low cutoff frequency filter, desired, for example, in biomedical applications.A look-up table model is used, with the experimental device data as input, which is reported to have an accurate response comparing to the measurements.The design of an operational amplifier circuit, the main part of a Gm-C filter, is presented, where around 100 dB voltage gain with two-stage topology is obtained. The filter showed a 100 Hz cutoff frequency response with 36 nW pole−1 power consumption, which represents a significant improvement in comparison to recently reported designs using CMOS technology.

Practical Design of an 80 MHz Bandpass Gm-C Filter with a Digital Tuning Scheme

Background: Growing wireless communication market is forcing the engineers to design portable and cheaper devices. This could be completed by reducing power consumption and saving battery life. Objective: In this study, a bandpass filter with a central frequency of 80 MHz with the ability to digitally tune the central frequency was designed and simulated. OTA-C blocks (gm-C) were utilized to implement the filter. For this purpose, instead of using a fixed capacitor, we use an array of voltage-variable capacitors that are placed in the form of a capacitor bank. Results: The proposed filter was implemented at the transistor level with 180 nm CMOS technology and simulated with the RF H-spice software. In the proposed filter, the bandwidth of 20 MHz was digitally tuned by 1 MHz increments. The average power consumption at the center frequency of 80 MHz was equal to 24.23 mW. Conclusion: The practical analysis of the digitally tuning filter technique and the simulation results are explained. A comparison of the performance parameters of the simulated filter with state-of-the-art filters indicates that the proposed filter can change its bandwidth over a wide range with the lower power consumption and the lower noise.

Low power analogue equaliser with adaptive digital tuning for fast ethernet

This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g m -C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three operational transconductance amplifiers (OTAs) are merged into a novel multi-input OTA structure. Additionally, a robust digital control logic is presented to automatically adjust the parameters of the equaliser for different cable lengths. A fast settling time below 250 µs is demonstrated for different scenarios. The equaliser is fabricated as part of a Fast Ethernet PHY chip in a 180 nm CMOS technology of GLOBALFOUNDRIES. Measurement results demonstrate error-free data transmission (bit error rate below 10 −12 ) for cable lengths up to 120 m. The power consumption of the analogue equaliser ranges from 2.3 mW (short cable) to 6.5 mW (120 m cable). To the best of the authors’ knowledge, this is the lowest power consumption of an analogue equaliser for Fast Ethernet, supporting additional BLW and flat loss compensation reported to date.

A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

Realization of Analog Wavelet Filter Using Hybrid Genetic Algorithm for On-Line Epileptic Event Detection

As the evolution of traditional electroencephalogram (EEG) monitoring unit for epilepsy diagnosis, wearable ambulatory EEG (WAEEG) system transmits EEG data wirelessly, and can be made miniaturized, discrete and social acceptable. To prolong the battery lifetime, analog wavelet filter is used for epileptic event detection in WAEEG system to achieve on-line data reduction. For mapping continuous wavelet transform to analog filter implementation with low-power consumption and high approximation accuracy, this paper proposes a novel approximation method to construct the wavelet base in analog domain, in which the approximation process in frequency domain is considered as an optimization problem by building a mathematical model with only one term in the numerator. The hybrid genetic algorithm consisting of genetic algorithm and quasi-Newton method is employed to find the globally optimum solution, taking required stability into account. Experiment results show that the proposed method can give a stable analog wavelet base with simple structure and higher approximation accuracy compared with existing method, leading to a better spike detection accuracy. The fourth-order Marr wavelet filter is designed as an example using Gm-C filter structure based on LC ladder simulation, whose power consumption is only 33.4 pW at 2.1Hz. Simulation results show that the design method can be used to facilitate low power and small volume implementation of on-line epileptic event detector.