Globally Asynchronous And Locally Synchronous Research Articles

A Scheduled Based Argo NI NoC Using GALS Architecture for MPSOC

In this paper, we have designed and implemented a scheduling for the micro-architecture of Argo Network Interface (NI), works based on globally asynchronous and locally synchronous (GALS) which provides efficient area for a real time multiprocessor application platform and uses time division multiplexing for message passing between the multiprocessor cores. Statically scheduled TDM controls the network on chip structure to provide the guarantee over the real time multiprocessor application. GALS architecture contributes asynchronous routers collaborates scheduling and micro architecture together and results the data transformation in pipelined fashion from sending core to the receiving core of the local memory with none dynamic arbitration, clock synchronization and buffering. NI combines functionality of DMA, TDM and double ported memories to overcome from synchronization, buffering and control of flow rate. To substantiate the planning they have executed four-by-four bits in 65nm NoC CMOS mechanism then represented results on energy deletion, area and the speed for router, network on chip, post layout and network interface. Scheduling is done based on the resources like flit size, bandwidth, energy depletion etc., has been implemented. As a result the reliability of the argo NoC is elevated for more hard real-time applications.

Performance Enhancement Technique in Multiprocessors

Design of a programmable Multi core processor to implement compute several complex multimedia applications is presented. The Processor is expected to complete the given task with minimum latency. The hardware must adhere to minimal area and power requirements. This paper gives design details for enhancement of performance parameters of multi core processors. It is necessary to optimize the processor performance at both architectural and execution levels. At architectural level use of locally synchronous clocking mechanism will eliminate the use of global clock tree with the help of asynchronous handshake protocol. At execution level completion time is reduced by 30% with the concept of reconfigurable instruction set processor and parallelism at data, memory, instruction and task level. General Terms Multiprocessor, Instruction set, Globally asynchronous and locally synchronous (GALS), Multi Reconfigurable Instruction set processor system on chip (MRPSoC), Multigrain-MRPSoC, Reconfigurable Instruction set Processors (RISP), Multigrain parallelism.

Asynchronous Circuit Designs for the Internet of Everything: A Methodology for Ultralow-Power Circuits with GALS Architecture

Asynchronous circuits have characteristics that differ significantly from those of synchronous circuits in terms of their power and robustness to variations. In this article, we show how it is possible to exploit these characteristics to design robust ultralow-power circuits within the scope of the Internet of Everything (IoE) and with globally asynchronous and locally synchronous (GALS) architectures. More specifically, our aim is to describe the fundamentals of asynchronous circuit design; to detail specific methodologies with practical examples of low-power, asynchronous circuits; and to offer clear guidelines that differentiate the usefulness of an asynchronous circuit compared to a synchronous one according to different application needs.

Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework

As Globally Asynchronous and Locally Synchronous (GALS) based System-on-chip (SoC) are gaining importance, a special case of GALS when the global clocking is preserved, but the interconnect delays of multiple clock cycles are to be tolerated has also been proposed, and used. In some cases, such designs, known as Latency-Insensitive Protocol (LIP) based SoC integration are also general enough to work when the global clocking is not present. In either case, the protocols are complex, and many optimized implementations of such protocols need verification that indeed they work correctly with respect to the specification of the system. Usually the specification of the system is fully globally clocked with negligible interconnect delays, so that the specification can be first implemented as synchronous design with traditional tools. GALS or LIP refinements are then applied to tolerate the multi-cycle interconnect delays, or fully asynchronous interconnect communication, as the case may be. Verifying that such refinements are correctness preserving, researchers have used model checking in the past. In this paper, we present static analysis based framework for such verification. Our framework makes use of the Polychrony framework and associated semantic analysis techniques, in the form of endo-isochrony. We show a number of LIP protocols to preserve the correctness with respect to their fully synchronous specifications using our framework. We believe, designers can verify LIP implementations with clever optimizations using our framework much more readily than when using model checking.

An Analysis of the Composition of Synchronous Systems

Safety-critical embedded applications are often distributed. For example, software in an automotive control or in avionics control are distributed over a large number of distributed processors which are connected over some domain specific buses. Correctness of such applications is of paramount importance due to their safety-critical nature. Synchronous programming models (e.g. Esterel, SIGNAL, Lustre) make synchrony assumption (zero time intra-module computation and zero time inter module communication) while modeling such applications so that the model is easier to verify. Once verified, models built with such assumptions need to be distributed over an asynchronous communication based platform which brings out the challenge of Globally Asynchronous and Locally synchronous (GALS) design. The correctness preserving refinement of a fully synchronous model onto a globally asynchronous communication media implies that various restrictions be imposed on the synchronous model. In the realm of polychronous programming model (exemplified by the SIGNAL language), a property called ‘endo-isochrony’ was proposed in early 1990s. Endochrony of individual modules assures safe sequential code generation from the module specification, and isochrony ensures safe communication between modules. In this paper, first we provide a more general sufficient condition for isochrony. Second, we generalize the definition of isochrony for weakly-endochronous modules. Further, we introduce the notion of directional isochrony which provides sufficient conditions for safe communication between modules in one direction but not in the other direction. The results in this paper not only simplifies the understanding of the conditions under which a polychronous specification can be implemented in GALS, but also sheds interesting lights on causality and isochrony. When the synchronous modules are reused as IPs, the conditions described here can be checked to see whether those modules can be composed asynchronously with the same behavior as their synchronous composition.

Asynchronous Techniques for System-on-Chip Design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.

Special issue on formal methods for globally asynchronous and locally synchronous (GALS) systems

This special issue is based on innovative ideas presented and discussed during the first International Workshop on Formal Methods for Globally Asynchronous and Locally Synchronous Systems (FMGALS) held in conjunction with the Formal Methods in Europe (FME) conference in Pisa, Italy, in the fall of 2003. This one-day workshop was initiated to bring together researchers in the area of formal methods, system design languages, asynchronous hardware design, and GALS design. The event was held in co-operation with ACM SIGDA and ACM SIGARCH. Since this first incarnation, another FMGALS workshop was held in Verona, Italy in 2005. A special issue for that event is already planned. One great outcome of the first workshop is that an FMGALS community has been established through a moderated mailing list. Information and research result exchanges are taking place among the various research communities who are engaged in research aimed at providing theoretical foundations of GALS design, industrial GALS design practices, and de-synchronization theory proposed by the Synchronous Programming community. Selected papers from the 2003 workshop were invited for this special issue together with an open call for papers soliciting novel contributions on the topics of this conference. Rigorous reviews of 12 submissions led to the selection of five papers. In this editorial statement, we outline the premise and the context of this special issue, and briefly introduce the papers selected.

Introduction to the Special Section on Energy Efficient Computing

ENERGY efficient computing used to be a concern only for designers of untethered computer and mobile communication systems, where battery size and recharge intervals limited their usefulness. In the past few years, the importance of reducing energy has become a central concern for designers of tethered computers as well because of the power limitations of a standard household power outlet and because they are often deployed in large groups, in the case of server farms. To address the research issues that arise in energy efficient computing, the US Defense Advanced Projects Agency began a program several years ago under the heading Power Aware Computing and Communications (PAC/C). This has led to a wide range of new developments in energy efficient computing and communications. This special issue solicited original papers from, but not restricted to, researchers in the PAC/C program. Our goal was to show the wide range of computer related research that is concerned with minimizing energy consumption in one way or another. Our lead-off paper, “Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages,” employs genetic algorithm for module selection and scheduling under the constraints of power and area. The next paper, “Charge-Recovery Computing on Silicon,” presents an overview of energy-recovering systems, focusing on recent developments. The third paper, “A Holistic Approach to Designing Energy-Efficient Cluster Interconnects,” looks at interconnecting networks of computers and addresses the problem of designing the interconnects to be energy-efficient. The fourth paper, “Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors,” focuses on the microarchitectural level and proposes and analyzes a clustered loop buffer for VLIW-style processors. The analysis shows that such buffers are able to generate a significant amount of energy savings. The fifth paper in our series, “Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors,” moves to a higher level of abstraction and proposes a fast and efficient approach for designing and estimating energy consumption for single chip heterogeneous multiprocessors—a common platform for mobile system. The sixth paper, “An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs,” returns to the microarchitectural level. It proposes a design time instruction set minimization to reduce instruction cache power. The seventh paper, “Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations,” looks at the application level, specifically the power-performance of motion detection in an image processing application. The eighth paper, “Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes,” is a tutorial paper on sensor networks with special emphasis on their power requirements. The penultimate paper, “A Speculative Control Scheme for an Energy-Efficient Banked Register File,” again returns to the microarchitectural level and shows how low power register files can be constructed from smaller faster banks of registers. The last paper, “GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks,” proposes an adaptive scalable architecture targeted toward algorithm-specific tasks in which power is a constraint. The architectural model derives its scalability from a set of Globally Asynchronous and Locally Synchronous (GALS) building blocks.

GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks

Reducing the energy consumption of a real-time system has emerged as an important design concern. In this paper, we propose GAARP, an adaptive scalable architecture targeted toward algorithm-specific tasks for just-in-time performance using the right amount of power. The architecture consists of Globally Asynchronous and Locally Synchronous (GALS) building blocks, where the processing hardware is realized by a set of smaller slices of similar structure, each running synchronously with independent clocks. We demonstrate that, for different real-time commercial applications with algorithm-specific jobs like online transaction processing, digital filtering, Fourier transform, etc., the proposed architecture allows dynamic load-balancing and adaptive intertask voltage scaling based on the load in each of the processing units. Compared to a synchronous implementation of the same functionality, we show that the proposed hardware can achieve higher efficiency in terms of power and performance by exploiting the flexibility to balance the load and change the supply voltage. The architecture also lends itself to process tolerance since it can detect process-shifts for the individual processing units and determine the appropriate operating voltage/frequency for each unit. Simulation results for two representative applications show that, for a modest system configuration and random job distribution, we obtain up to 67 percent improvement in MOPS/W (millions of operations per second per watt) over a fully synchronous implementation.