A Scheduled Based Argo NI NoC Using GALS Architecture for MPSOC

Abstract

In this paper, we have designed and implemented a scheduling for the micro-architecture of Argo Network Interface (NI), works based on globally asynchronous and locally synchronous (GALS) which provides efficient area for a real time multiprocessor application platform and uses time division multiplexing for message passing between the multiprocessor cores. Statically scheduled TDM controls the network on chip structure to provide the guarantee over the real time multiprocessor application. GALS architecture contributes asynchronous routers collaborates scheduling and micro architecture together and results the data transformation in pipelined fashion from sending core to the receiving core of the local memory with none dynamic arbitration, clock synchronization and buffering. NI combines functionality of DMA, TDM and double ported memories to overcome from synchronization, buffering and control of flow rate. To substantiate the planning they have executed four-by-four bits in 65nm NoC CMOS mechanism then represented results on energy deletion, area and the speed for router, network on chip, post layout and network interface. Scheduling is done based on the resources like flit size, bandwidth, energy depletion etc., has been implemented. As a result the reliability of the argo NoC is elevated for more hard real-time applications.