Global Wires Research Articles

Centip3De

Process scaling has resulted in an exponential increase of the number of transistors available to designers. Meanwhile, global interconnect has not scaled nearly as well, because global wires scale only in one dimension instead of two, resulting in fewer, high-resistance routing tracks. This paper evaluates the use of three-dimensional (3D) integration to reduce global interconnect by adding multiple layers of silicon with vertical connections between them using through-silicon vias (TSVs). Because global interconnect can be millimeters long, and silicon layers tend to be only tens of microns thick in 3D stacked processes, the power and performance gains by using vertical interconnect can be substantial. To address the thermal issues that arise with 3D integration, this paper also evaluates the use of near-threshold computing---operating the system at a supply voltage just above the threshold voltage of the transistors. Specifically, we will discuss the design and test of Centip3De, a large-scale 3D-stacked near-threshold chip multiprocessor. Centip3De uses Tezzaron's 3D stacking technology in conjunction with Global Foundries' 130 nm process. The Centip3De design comprises 128 ARM Cortex-M3 cores and 256MB of integrated DRAM. Silicon measurements are presented for a 64-core version of the design.<!-- END_PAGE_1 -->

Scalable high-radix router microarchitecture using a network switch organization

As the system size of supercomputers and datacenters increases, cost-efficient networks become critical in achieving good scalability on those systems. High -radix routers reduce network cost by lowering the network diameter while providing a high bisection bandwidth and path diversity. The building blocks of these large-scale networks are the routers or the switches and they need to scale accordingly to the increasing port count and increasing pin bandwidth. However, as the port count increases, the high-radix router microarchitecture itself needs to scale efficiently. Hierarchical crossbar switch organization has been proposed where a single large crossbar used for a router switch is partitioned into many small crossbars and overcomes the limitations of conventional router microarchitecture. Although the organization provides high performance, it has limited scalability due to excessive power and area overheads by the wires and intermediate buffers. In this article, we propose scalable router microarchitectures that leverage a network within the switch design of the high-radix routers themselves. These alternative designs lower the wiring complexity and buffer requirements. For example, when a folded-Clos switch is used instead of the hierarchical crossbar switch for a radix-64 router, it provides up to 73%, 58%, and 87% reduction in area, energy-delay product, and energy-delay-area product, respectively. We also explore more efficient switch designs by exploiting the traffic-pattern characteristics of the global network and its impact on the local network design within the switch for both folded-Clos and flattened butterfly networks. In particular, we propose a bilateral butterfly switch organization that has fewer crossbars and global wires compared to the topology-agnostic folded-Clos switch while achieving better low-load latency and equivalent saturation throughput.

Board- and Chip-Aware Package Wire Planning

The slow turnaround between design, package, and system houses has been one of the primary concerns in the semiconductor business. There is a serious lag in the development time of the systems due to time-consuming interface design between the chip, package, and board. In order to enable chip-package-board codesign to speed up the design process, we propose an approach to address this issue by efficiently planning wires for board and chip design awareness, which includes the package pin-out designation and the corresponding wire planning in package and board. We model the problem as an interval intersection problem. Because of the special need in pin-out rules, an algorithm to resolve the problem is developed. We then use some optimization techniques to further improve objectives such as global wire congestion and length deviation. Our results show that a very efficient estimation can be made considering those important objectives, and package congestion can be successfully mitigated.

Intrinsic gray-matter connectivity of the brain in adults with autism spectrum disorder

Autism spectrum disorders (ASD) are a group of neurodevelopmental conditions that are accompanied by atypical brain connectivity. So far, in vivo evidence for atypical structural brain connectivity in ASD has mainly been based on neuroimaging studies of cortical white matter. However, genetic studies suggest that abnormal connectivity in ASD may also affect neural connections within the cortical gray matter. Such intrinsic gray-matter connections are inherently more difficult to describe in vivo but may be inferred from a variety of surface-based geometric features that can be measured using magnetic resonance imaging. Here, we present a neuroimaging study that examines the intrinsic cortico-cortical connectivity of the brain in ASD using measures of "cortical separation distances" to assess the global and local intrinsic "wiring costs" of the cortex (i.e., estimated length of horizontal connections required to wire the cortex within the cortical sheet). In a sample of 68 adults with ASD and matched controls, we observed significantly reduced intrinsic wiring costs of cortex in ASD, both globally and locally. Differences in global and local wiring cost were predominantly observed in fronto-temporal regions and also significantly predicted the severity of social and repetitive symptoms (respectively). Our study confirms that atypical cortico-cortical "connectivity" in ASD is not restricted to the development of white-matter connections but may also affect the intrinsic gray-matter architecture (and connectivity) within the cortical sheet. Thus, the atypical connectivity of the brain in ASD is complex, affecting both gray and white matter, and forms part of the core neural substrates underlying autistic symptoms.

HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-onChip (SoC) implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC) architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS) Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared

Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors

For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

The Bluetooth Honeypot Project

Bluetooth technology (BT) and the inherent security vulnerabilities it introduces into business domains are often overlooked when security policies are developed. However, the International Data Corporation (IDC) projected that global Bluetooth short-wave wire semiconductor revenue will triple from $1.7 billion in 2007, to $3.3 billion in 2012 (Reidy, 2008). After a brief history of Bluetooth technology, researchers will examine how Bluetooth works, its vulnerabilities, and how these vulnerabilities can be exploited. Bluetooth malware and its associated risks will also be explored. As a practical approach to monitor Bluetooth threats and malware, the employment of a Bluetooth honeypot will be discussed, including honeypot structure and the legalities of deploying them. Building on Andrew Smith’s earlier work developing Bluepot, a functional Bluetooth honeypot (Smith, 2011), researchers will test Bluepot and discuss the feasibility of using it as a prototype for developing a functional Bluetooth honeypot to secure corporate data and analyze BT malware.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy–performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy–delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure.

Power profiling-guided floorplanner for 3D multi-processor systems-on-chip

Three-dimensional (3D) integration has become one of the most promising techniques for the development of future multi-core processors, since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems because the closer proximity of heat generating dies makes existing thermal hotspots more severe. Thermal-aware floorplanners can play an important role to improve the thermal profile, but they have failed in considering the dynamic power profiles of the applications. This study proposes a novel thermal-aware floorplanner guided by the power profiling of a set of benchmarks that are representative of the application scope. The results show how our approach outperforms the thermal metrics as compared with the worst-case scenario usually considered in ‘traditional’ thermal-aware floorplanners.

Analysis and Optimization of Thermal-Driven Global Interconnects in Nanometer Design

Global interconnects play an increasingly important role in nanometer-scale integrated technologies. The optimization of global wire size (width and/or spacing) has been well studied. However, many optimization methodologies do not consider thermal effects. As technology scales, decreasing interconnect pitch and the introduction of low-k dielectrics have made self-heating of global interconnects an important issue. In this paper, we present a temperature-aware methodology for systematically optimizing the size of global interconnects with optimal repeater for maximizing the circuit performance. We develop techniques to calculate the full-chip temperature as a function of global interconnect width and spacing and analytically analyze the impacts of wire size on the substrate and self-heating temperature. We then reinvestigate the temperature -and size-dependent interconnect delay, bandwidth, and power consumption, and define a product of the delay per unit length, power dissipation per unit length, and reciprocal bandwidth per unit chip edge as an appropriate figure of merit for optimum wire size for various International Technology Roadmap for Semiconductors technology nodes.

Interconnect Network Analysis of Many-Core Chips

This paper presents the first intercore interconnect technology optimization and wiring demand calculation for mesh, concentrated mesh, flattened butterfly, and concentrated flattened butterfly network-on-chip topologies. Global wire dimensions are optimized to achieve maximum bandwidth and minimum delay. The core-to-core channel width is then determined by taking into account the available wiring area and area occupied by the router within each core. It is shown that the router area limits the channel width for all topologies. In mesh and concentrated mesh topologies, a smaller channel width results in underutilization of the available wiring area; less than 10% of the area available in two orthogonal wiring levels if the router area is constrained to 20% of the core area. For flattened butterfly and concentrated flattened butterfly topologies, the required wiring areas can be as high as 80% of two orthogonal wiring levels for the same routing area constraint. However, flattened butterfly topology does not scale for a larger number of cores due to the rapid increase in the number of ports and, consequently, router area.

Prediction and Comparison of High-Performance On-Chip Global Interconnection

As process technology scales, numerous interconnect schemes have been proposed to mitigate the performance degradation caused by the scaling of on-chip global wires. In this paper, we review current on-chip global interconnect structures and develop simple models to analyze their architecture-level performance. We propose a general framework to design and optimize a new category of global interconnect based on on-chip transmission line (T-line) technology. We perform a group of experiments using six different global interconnection structures to discover their differences in terms of latency, energy per bit, throughput, area, and signal integrity over several technology nodes. Our results show that T-line structures have the potential to outperform conventional repeated RC wires at future technology nodes to achieve higher performance while using less power and improving the reliability of wire communication. Our results also show that on-chip equalization is helpful to improve throughput, signal integrity, and power efficiency.

A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors

Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible nanophotonics has emerged as a leading candidate for replacing global wires beyond the 16nm timeframe, on-chip optical interconnect architectures are typically limited in scalability or are dependent on comparatively slow electrical control networks. In this article, we present a hybrid electrical/optical router for future large scale, cache coherent multicore microprocessors. The heart of the router is a low-latency optical crossbar that uses predecoded source routing and switch state preconfiguration to transmit cache-line-sized packets several hops in a single clock cycle under contentionless conditions. Overall, our optical router achieves 2X better network performance than a state-of-the-art electrical baseline in a mesh topology while consuming 30% less network power.

Interconnect Design Challenges in Nano CMOS Circuit

In the conventional scaling scheme, interconnect delay cannot be reduced and the global interconnect delay become worse if the length of the wire is not scaled. The conventional approaches of global interconnect design are (1)introduction of inverse scaling concept where the upper metal layers have larger cross sections than lower metal layers, (2)insertion of repeaters, and (3) architecture level approach of multi/many core. In order to improve global interconnect delay even in aggressively miniaturized circuit, we have developed the transmission lien interconnect. This paper describes the novel analytical interconnect length distribution and discussion on future interconnect design direction. Then, recent our developments of the transmission line interconnect are described and performance comparison with another global wiring scheme such as optical interconnection is discussed.

Topology Synthesis for Low Power Cascaded Crossbar Switches

Crossbar switch network has an increasing impact on such critical measures as throughput, latency, area, and power consumption of complex system-on-chip as technology scales to deep submicrometer. With high clock frequency crossbar switch network design, global wire delay and pipeline registers inserted for throughput are important because they affect area, frequency, and power consumption of the chip. The traffic congestion is also a very important factor because it leads to the lowering of throughput of the crossbar switch network. In this paper, we present a topology synthesis method for the low-power cascaded crossbar switch network satisfying the given bandwidth, latency, frequency, and area constraints. Unlike previous papers, our paper considers wire delay, traffic congestion, and pipeline register insertion at the same time. Experimental results show that the topologies optimized for power consumption for a given clock frequency consume less power than existing methods by up to 38.04%.

동적 주파수 조절 기법을 적용한 3D 구조 멀티코어 프로세서의 온도 분석

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms

Networks-on-Chip (NoCs) can be used for test data transportation during manufacturing tests. On one hand, NoC can avoid dedicated Test Access Mechanisms (TAMs), reducing long global wires, and potentially simplifying the layout. On the other hand, (a) it is not known how much wiring is saved by reusing NoCs as TAMs, (b) the impact of reuse-based approaches on test time is not clear, and (c) a computer aided test tool must be able to support different types of NoC designs. This paper presents a test environment where the designer can quickly evaluate wiring and test time for different test architectures. Moreover, this paper presents a new test scheduling algorithm for NoC TAMs which does not require any NoC timing detail and it can easily model NoCs of different topologies. The experimental results evaluate the proposed algorithm for NoC TAMs with an exiting algorithm for dedicated TAMs. The results demonstrate that, on average, 24% (up to 58%) of the total global wires can be eliminated if dedicated TAMs are not used. Considering the reduced amount of dedicated test resources with NoC TAM, the test time of NoC TAM is only, on average, 3.88% longer compared to dedicated TAMs.

Hypothesis-driven structural connectivity analysis supports network over hierarchical model of brain architecture

The brain is usually described as hierarchically organized, although an alternative network model has been proposed. To help distinguish between these two fundamentally different structure-function hypotheses, we developed an experimental circuit-tracing strategy that can be applied to any starting point in the nervous system and then systematically expanded, and applied it to a previously obscure dorsomedial corner of the nucleus accumbens identified functionally as a "hedonic hot spot." A highly topographically organized set of connections involving expected and unexpected gray matter regions was identified that prominently features regions associated with appetite, stress, and clinical depression. These connections are arranged as a longitudinal series of circuits (closed loops). Thus, the results do not support a rigidly hierarchical model of nervous system organization but instead indicate a network model of organization. In principle, the double-coinjection circuit tracing strategy can be applied systematically to the rest of the nervous system to establish the architecture of the global structural wiring diagram, and its abstraction, the connectome.

Software Prepromotion for Non-Uniform Cache Architecture

As a solution to growing global wire delay, non-uniform cache architecture (NUCA) has already been a trend in large cache designs. The access time of NUCA is determined by the distance between the cache bank containing the required data and the processor. Thus, one of the important NUCA researches focuses on how to place data to be used into cache banks close to the processor. This paper proposes software prepromotion technique, which prepromote data using prepromotion instructions as similar as software prefetching does. Besides the basic software prepromotion, this paper also proposes smart multihop software prepromotion (SMSP), very long software prepromotion (VLSP) and their combination technique. SMSP intelligently chooses cache banks which the prepromoted data most ideally suit to being moved into. And VLSP prepromote multiple data using one instruction. Finally, we evaluate our approaches by testing 7 kernel benchmarks on a full-system simulator. The basic software prepromotion gets an average improvement of 2.6893% in IPC. The SMSP improves IPC by 7.0928% averagely. And the VLSP gets an IPC improvement of 7.2194% averagely. Lastly, after combining the SMSP and VLSP, the average improvement in IPC achieves 11.8650%.

Prediction of Self-Heating in Short Intra-Block Wires

This paper investigates whether the self-heating effect in short intra-block wires will become apparent with technology scaling. These wires seem to have good thermal radiation characteristics, but we validate that the self-heating effect in local signal wires will be greater than that in optimal repeater-inserted global wires. Our numerical experiment shows that the maximum temperature increase from the silicon junction temperature will reach 40.4°C in a steady state at a 14-nm process. Our attribution analysis also demonstrates that miniaturizing the area of wire cross-section exacerbates self-heating as well as using low-κ material and increased power dissipation in advanced technologies below 28nm. It is revealed that the impact of self-heating on performance in local wires is limited, while underestimating the temperature may cause an unexpected reliability failure.