Global Routing Problem Research Articles

A Very Large-Scale Integration Global Routing Optimization Model for Hybrid Physarum Bionetworks

Interconnection of billion transistors in a single layer of a die with the advent of the nanometer regime imposes a great challenge to handle the increased complexity, particularly in the global routing of the Very Large-Scale Integration (VLSI) physical design phase which involves distinct optimization in the computation of overall interconnect wire-length. In classical graph theory, the VLSI global routing problem can be mapped as a Rectilinear Steiner Minimal Tree (RSMT) Problem, which in itself is an NP-complete problem. The use of metaheuristics in solving this problem plays a major role where Ant Colony Optimization (ACO) and Particle Swarm Optimization (PSO) proved to be efficient algorithms. Both algorithms face certain limitations and inconsistencies in determining maximum optimization. A new optimization algorithm with insight from the biological activity of microorganisms has been proposed in this paper which is based on the behavior of the unicellular organism Physarum Polycephalum aiming at minimizing the wire length of VLSI interconnects. The paper further explores a new hybridization technique employing the use of Physarum BioNetwork and Particle Swarm Optimization together where PSO generate better possible Steiner’s in the initial stage for the final process using Physarum BioNetwork to ensure better convergence. Complexity analysis of the proposed algorithm has been performed and the simulation results achieved greater efficiency when compared with the conventional PSO algorithm and available industry benchmark over-optimizing Global Routing problem in VLSI design.

An Enhanced Deep Reinforcement Learning-Based Global Router for VLSI Design

Global routing is a crucial step in the design of Very Large-Scale Integration (VLSI) circuits. However, most of the existing methods are heuristic algorithms, which cannot conjointly optimize the subproblems of global routing, resulting in congestion and overflow. In response to this challenge, an enhanced Deep Reinforcement Learning- (DRL-) based global router has been proposed, which comprises the following effective strategies. First, to avoid the overestimation problem generated by Q -learning, the proposed global router adopts the Double Deep Q -Network (DDQN) model. The DDQN-based global router has better performance in wire length optimization and convergence. Second, to avoid the agent from learning redundant information, an action elimination method is added to the action selection part, which significantly enhances the convergence performance of the training process. Third, to avoid the unfair allocation problem of routing resources in serial training, concurrent training is proposed to enhance the routability. Fourth, to reduce wire length and disperse routing resources, a new reward function is proposed to guide the agent to learn better routing solutions regarding wire length and congestion standard deviation. Experimental results demonstrate that the proposed algorithm outperforms others in several important performance metrics, including wire length, convergence performance, routability, and congestion standard deviation. In conclusion, the proposed enhanced DRL-based global router is a promising approach for solving the global routing problem in VLSI design, which can achieve superior performance compared to the heuristic method and DRL-based global router.

Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction

The aggressive scaling down of the feature size in modern ICs has introduced major bottlenecks in printing layouts using a conventional 193nm immersion lithography system. As different mitigation techniques have reached their limitations, Next Generation Lithography (NGL) techniques have been gaining popularity. Extreme Ultra-violet Lithography (EUVL) system which uses light having 13.5nm wavelength is one of the popular NGL for printing features below 20nm. However, EUVL faces the problem of flare caused by irregular reflection from clear-field mask surfaces used. It leads to distortion of critical dimension (CD) during layout printing which in turn degrades the performance of the circuit. In this paper, we have formulated a delay-aware global routing problem in order to minimize flare without sacrificing the delay. Two different solvers, namely ILP and SAT-SMT, are employed and the results are compared. Experimental results show a significant reduction in flare without much compromise on delay.

Применение нейронных сетей для сегментации изображений в задаче быстрой трассировки интегральных схем

The paper explores the possibilities of using neural network methods to solve the problem of global routing for VLSI ASIC design. An algorithm has been developed for generating a training dataset based on the Lee algorithm, which allows one to synthesize three-dimensional matrices with obstacles and points that need to be connected. The U-Net fully convolutional neural network, effective for semantic segmentation of images, was selected for training. The quality of the results was assessed using a validation data. A significant reduction in routing time compared to the Lee algorithm was shown, but the share of unbroken routes was only 37%. Ways to improve the training dataset and adapt the approach to real conditions using DEF and GUIDE files are proposed. In general, the work demonstrated the potential of neural network methods to speed up the global routing task, but continued research is required to improve the quality and reliability of the results. The work is useful for specialists in the field of integrated circuit design and machine learning.

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

PurposeAdvancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO).Design/methodology/approachThis paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark.FindingsThis paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits.Practical implicationsThis paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms.Originality/valueThis paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

A Deep Reinforcement Learning Approach for Global Routing

Abstract Global routing has been a historically challenging problem in the electronic circuit design, where the challenge is to connect a large and arbitrary number of circuit components with wires without violating the design rules for the printed circuit boards or integrated circuits. Similar routing problems also exist in the design of complex hydraulic systems, pipe systems, and logistic networks. Existing solutions typically consist of greedy algorithms and hard-coded heuristics. As such, existing approaches suffer from a lack of model flexibility and usually fail to solve sub-problems conjointly. As an alternative approach, this work presents a deep reinforcement learning method for solving the global routing problem in a simulated environment. At the heart of the proposed method is deep reinforcement learning that enables an agent to produce a policy for routing based on the variety of problems, and it is presented with leveraging the conjoint optimization mechanism of deep reinforcement learning. Conjoint optimization mechanism is explained and demonstrated in detail; the best network structure and the parameters of the learned model are explored. Based on the fine-tuned model, routing solutions and rewards are presented and analyzed. The results indicate that the approach can outperform the benchmark method of a sequential A* method, suggesting a promising potential for deep reinforcement learning for global routing and other routing or path planning problems in general. Another major contribution of this work is the development of a global routing problem sets generator with the ability to generate parameterized global routing problem sets with different size and constraints, enabling evaluation of different routing algorithms and the generation of training datasets for future data-driven routing approaches.

A unified algorithm based on HTS and self-adapting PSO for the construction of octagonal and rectilinear SMT

The Steiner minimal tree (SMT) problem is an NP-hard problem, which is the best connection model for a multi-terminal net in global routing problem. This paper presents a unified algorithm for octagonal and rectilinear SMT construction based on hybrid transformation strategy (HTS) and self-adapting particle swarm optimization. Firstly, an effective HTS is proposed to enlarge the search space and improve the convergence speed. Secondly, the proposed HTS in the evolutionary process may produce an ineffective solution, and consequently the crossover and mutation operators of genetic algorithm (GA) based on union-find sets is proposed. Thirdly, a self-adapting strategy that can adjust the acceleration coefficients is proposed to further improve the convergence and the quality of the proposed algorithm. Finally, the hybrid transformation can be applied to GA and the proposed algorithm can be applied to rectilinear architecture. To our best knowledge, the proposed algorithm is the first unified algorithm to solve the SMT construction under both octagonal and rectilinear architecture. The experimental results show that the proposed algorithm can efficiently provide a better solution for SMT problem both in octagonal and rectilinear architectures than others. Moreover, the algorithm can obtain several topologies of SMT, which is beneficial for optimizing congestion in VLSI global routing stage.

A Game Theory Based Post-Processing Method to Enhance VLSI Global Routers

The increase in problem size and complexity of the global routing problems has made it harder for the global routers to produce good results. The global routers employ many different techniques to reach good solutions. However, the results on the recent benchmarks (ISPD 2008) reveal that existing global routers need more enhancements in their designs in-order to improve their solution quality. This work proposes a game theory based algorithm that can enhance the solutions of existing global routers. The proposed algorithm models the rip-up and re-route process as a sequential game in which nets act as players. The set of pure strategies of a net consists of different methods to rip-up and re-route its spanning tree. The nets use mixed strategies in which the probability of any pure strategy is based on the estimation of its likelihood to improve the solution. The performance of the proposed method has been evaluated by using it to enhance the solutions of two excellent global routers namely NCTU-GR 2.0 [1] & BFG-R [2] . The proposed method has been experimented using the ISPD 2008benchmarks and found to be successful in enhancing the total-overflow/wire-length of the existing global routers. On four hard-to-route problems, it has improved the total-overflow of three problems when used with NCTU-GR 2.0 and all four problems when used with BFG-R. It has improved the wire-lengths of all sixteen problems for both NCTU-GR 2.0 and BFG-R. The wire-length of NCTU-GR 2.0 was improved by a value ranging from 35–754 edges and that of BFG-R by a value ranging from 6462–15587 edges. While we demonstrated the potential of GT to enhance results of other heuristics, embedding the discussed technique can help produce better global routers as it will help better traversal of search space, and intelligent decision making.

A stochastic evolution algorithm based 2D VLSI global router

In this work we present a global router that uses the features of the Stochastic Evolution (StocE) algorithm to perform the rip-up and re-route (R&R) process. The unique features of the proposed global router are its simple design and ability to produce good results. It has two main components: (i) maze routing with framing (MRF) that act as a means of routing the nets; and (ii) a StocE algorithm that controls the R&R process and adjusts the parameters of the MRF method. This work shows that the StocE algorithm can perform the net selection in the R&R process and also adjust the parameter values of the MRF method in order to successfully solve 2D global routing problems. The performance of the proposed global router on the ISPD98 and ISPD2008 benchmarks was found to be better than some of the existing global routers.

XGRouter: high-quality global router in X-architecture with particle swarm optimization

This paper presents a high-quality very large scale integration (VLSI) global router in X-architecture, called XGRouter, that heavily relies on integer linear programming (ILP) techniques, partition strategy and particle swarm optimization (PSO). A new ILP formulation, which can achieve more uniform routing solution than other formulations and can be effectively solved by the proposed PSO is proposed. To effectively use the new ILP formulation, a partition strategy that decomposes a large-sized problem into some small-sized sub-problems is adopted and the routing region is extended progressively from the most congested region. In the post-processing stage of XGRouter, maze routing based on new routing edge cost is designed to further optimize the total wire length and mantain the congestion uniformity. To our best knowledge, XGRouter is the first work to use a concurrent algorithm to solve the global routing problem in X-architecture. Experimental results show that XGRouter can produce solutions of higher quality than other global routers. And, like several state-of-the-art global routers, XGRouter has no overflow.

A Game Theory-Based Heuristic for the Two-Dimensional VLSI Global Routing Problem

In this work we propose a game theory (GT)-based global router. It works in two steps: (i) Initial routing of all nets using maze routing with framing (MRF) and (ii) GT-based rip-up and reroute (R&R) process. In initial routing, the nets are divided into several small subsets which are routed concurrently using multithreading (MT). The main task of the GT-based R&R process is to eliminate congestion. Nets are considered as players and each player employs two pure strategies: (attempt to improve its spanning tree, and, do not attempt to improve its spanning tree). The nets also have mixed strategies whose values act as probabilities for them to select any particular pure strategy. The nets which select their first strategy will go through the R&R operation. We also propose an algorithm which computes the mixed strategies of nets. The advantage of using GT to select nets is that it reduces the number of nets and the number of iterations in the R&R process. The performance of the proposed global router was evaluated on ISPD'98 benchmarks and compared with two recent global routers, namely, Box Router 2.0 (configured for speed) and Side-winder. The results show that the proposed global router with MT has a shorter runtime to converge to a valid solution than that of Box Router 2.0. It also outperforms Side-winder in terms of routability. The experimental results demonstrated that GT is a valuable technique in reducing the runtime of global routers.

Exploring High-Throughput Computing Paradigm for Global Routing

With aggressive technology scaling, the complexity of the global routing problem is poised to grow rapidly. Solving such a large computational problem demands a high-throughput hardware platform such as modern graphics processing units (GPUs). In this paper, we explore a hybrid GPU-CPU high-throughput computing environment as a scalable alternative to the traditional CPU-based router. We introduce net-level concurrency (NLC), which is a novel parallel model for router algorithms and aims to exploit concurrency at the level of individual nets. To efficiently uncover NLC, we design a scheduler to create groups of nets that can be routed in parallel. At its core, our scheduler employs a novel algorithm to dynamically analyze data dependencies between multiple nets. We believe such an algorithm can lay the foundation for uncovering data-level parallelism in routing, which is a necessary requirement for employing high-throughput hardware. Detailed simulation results show an average of 4× speedup over NTHU-Route 2.0 with negligible loss in solution quality. To the best of our knowledge, this is the first work on utilizing GPUs for global routing.

The method for global routing of submicron VLSIs based on the use of the family of the steiner trees

The method for the solution of the problem of global routing of signal VLSI circuits based on the use of the family of Steiner trees for each circuit is described. The method makes it possible to minimize both the circuit length and the local routing density. The results of the investigation of this method are presented.

A Multilevel Congestion-Based Global Router

Routing in nanometer nodes creates an elevated level of importance for low-congestion routing. At the same time, advances in mathematical programming have increased the power to solve complex problems, such as the routing problem. Hence, new routing methods need to be developed that can combine advanced mathematical programming and modeling techniques to provide low-congestion solutions. In this paper, a hierarchical mathematical programming-based global routing technique that considers congestion is proposed. The main contributions presented in this paper include (i) implementation of congestion estimation based on actual routing solutions versus purely probabilistic techniques, (ii) development of a congestion-based hierarchy for solving the global routing problem, and (iii) generation of a robust framework for solving the routing problem using mathematical programming techniques. Experimental results illustrate that the proposed global router is capable of reducing congestion and overflow by as much as 36% compared to the state-of-the-art mathematical programming models.

Fashion: A Fast and Accurate Solution to Global Routing Problem

This paper presents a fast and accurate solution, namely Fashion, to routability-driven global routing problem. Fashion is based on two efficient yet effective techniques: 1) dynamic pattern routing (DPR) and 2) movable-segment-driven DPR. These two techniques enable Fashion to explore large solution space to achieve high routability with low time complexity. Compared with BoxRouter, Fashion has a shorter wire length and reduces overflow and runtime by 5 and 15 times, respectively. Compared with FastRoute, Fashion has similar runtime but 90% smaller overflow and 1.9% shorter wire length. Fashion is significantly better than Labyrinth and Fengshui in terms of overflow, wire length, and runtime.

On routing in VLSI design and communication networks

In this paper, we study the global routing problem in VLSI design and the multicast routing problem in communication networks. First we propose new and realistic models for both problems. In the global routing problem in VLSI design, we are given a lattice graph and subsets of the vertex set. The goal is to generate trees spanning these vertices in the subsets to minimize a linear combination of overall wirelength (edge length) and the number of bends of trees with respect to edge capacity constraints. In the multicast routing problem in communication networks, a graph is given to represent the network, together with subsets of the vertex set. We are required to find trees to span the given subsets and the overall edge length is minimized with respect to capacity constraints. Both problems are APX -hard. We present the integer linear programming (LP) formulation of both problems and solve the LP relaxations by the fast approximation algorithms for min–max resource-sharing problems in [K. Jansen, H. Zhang, Approximation algorithms for general packing problems and their application to the multicast congestion problem, Math. Programming, to appear, doi: 10.1007/s10107-007-0106-8] (which is a generalization of the approximation algorithm proposed by Grigoriadis and Khachiyan [Coordination complexity of parallel price-directive decomposition, Math. Oper. Res. 2 (1996) 321–340]). For the global routing problem, we investigate the particular property of lattice graphs and propose a combinatorial technique to overcome the hardness due to the bend-dependent vertex cost. Finally, we develop asymptotic approximation algorithms for both problems with ratios depending on the best known approximation ratio for the minimum Steiner tree problem. They are the first known theoretical approximation bound results for the problems of minimizing the total costs (including both the edge and the bend costs) while spanning all given subsets of vertices.

Block-level 3-D Global Routing With an Application to 3-D Packaging

Three-dimensional (3-D) packaging via system-on-a-package (SOP) has been recently proposed as an alternative solution to overcome the limitation of system-on-a-chip (SOC) and meet the rigorous requirements of today's mixed signal system integration. The true potential of SOP technology lies in its capability to integrate both active and passive components into a single high speed/density 3-D packaging substrate. The routing environment for 3-D SOP is more advanced than that of the conventional printed circuit board (PCB) or multichip module (MCM) technology - pins are located at all layers of the SOP packaging substrate rather than the topmost layer only, and various types of vias are available for layer-to-layer connections. The contribution of this work is to provide: 1) the formulation of the new block-level 3-D global routing problem under wire length, layer, crosstalk, and congestion minimization and 2) the first global router for 3-D SOP named 3PGR. This paper reviews various approaches for MCM routing algorithms and investigates their applicability to the SOP model. The related experimental results demonstrate the effectiveness of the algorithms

Integer Linear Programming Models for Global Routing

Modern integrated circuit design involves the layout of circuits consisting of millions of switching elements or transistors. Due to the sheer complexity of the problem, optimizing the connectivity between transistors is very difficult. The circuit interconnection is the single most important factor in performance criteria such as signal delay, power dissipation, circuit size, and cost. These factors dictate that interconnections, i.e., wires, be made as short as possible. The wire-minimization problem is generally formulated as a sequence of discrete optimization subproblems that are known to be NP-hard. Hence, they can only be solved approximately using meta-heuristics. These methods are computationally expensive and the quality of the solution depends to a great extent on an appropriate choice of starting configuration and modeling techniques. In this paper, new modeling techniques are used to solve the routing problem formulated as an integer programming problem. The main contribution of this paper is a proposed global routing heuristic that combines the wire length, channel congestion, and number of pins in routes to find the best wiring layout of a circuit. By adding information such as channel congestion and the number of pins in each route as well as the wire length, the quality of the solution is improved. In addition, the solutions of the large relaxed linear programming problems are skewed towards a zero-one solution, resulting in faster convergence. The developed LP models in this paper are useful when solving the global routing problem for two reasons; first, the new interior-point algorithms to solve the LP problem are polynomial in time. Second, “near optimal wiring” is obtained in polynomial time without performing randomized rounding.

Extended global routing with RLC crosstalk constraints

In this paper, we study an extended global routing problem with RLC crosstalk constraints. Considering simultaneous shield insertion and net ordering, we propose a multiphase algorithm to synthesize a global routing solution with track assignment to satisfy the RLC crosstalk constraint at each sink. The key algorithm phase is global routing synthesis with shield reservation and minimization based on prerouting shield estimation. Experiments using large industrial benchmarks show that compared to the best alternative with postrouting shield insertion and net ordering, the proposed algorithm with shield reservation and minimization reduces the congestion by 18.4% with a smaller runtime. To the best of our knowledge, this is the first in-depth study on global routing synthesis with RLC crosstalk constraints.

Creating and exploiting flexibility in rectilinear steiner trees

The global routing problem decomposes the large, complex routing problem into a set of more manageable subproblems. The high correlation between the output of the global router and the detailed router enables the designer to efficiently use the global route to refine the design quickly before running the full detailed route. Hence, routability of the global routing solution is the key factor. The routability of the circuit depends on the congestion of the routing. In this paper, we study Steiner trees in terms of routability. We introduce the notion of flexibility, a geometric property associated with Steiner trees. We show that the flexibility of a Steiner tree is related to its routability. The main contribution of this paper is an algorithm which takes a stable Steiner tree as an input and maps it to a more flexible Steiner tree. Any existing Steiner tree algorithm can be used for the initial construction of the Steiner tree. Experiments with a global router on a subset of nets show that routing congestion is improved by approximately 20% locally throughout the region where those nets are routed.