Gigabit Ethernet Interface Research Articles

Методика проектирования сверхширокополосного цифрового приемника с субдискретизацией

UWB digital receiver design methodology with sub-Nyquist sampling in radio monitoring and cognitive radio tasks, processing of overlapped signals in an ultra-wide frequency band without gaps is required. A digital receiver with sub-Nyquist sampling allows solving this problem. However, in practice, we have some issues. There are various kinds of ambiguity in determining the frequency. The nonlinear elements of the path generate parasitic harmonics of the input signal. In the multi-signal mode, the discrimination of signals deteriorates. All this significantly reduces the efficiency of signal analysis. Therefore, a receiver circuit with software implemented means of eliminating the listed disadvantages is proposed. Such a receiver has features characteristic of sub-Nyquist sampling and selectable parameters. A special technique has been developed to systematize the design process of the receiver. The design methodology takes into account the use of the receiver in single-signal and multi-signal modes. The result of the design is the receiver block diagram with a justification of the parameters of its main elements. The proposed methodology makes it possible to evaluate system characteristics such as sensitivity, the number of processing channels and the throughput by the number of superimposed signals. Automation of checking the conditions given in the methodology can significantly increase the speed and convenience of design. It is shown that for the Gigabit Ethernet interface, the through put of the receiver is about eight superimposed pulse or continuous signals. In this case, due to parasitic components arising in the nonlinear elements of the path, it can be reduced to 4 superimposed signals. The actual number of processed signals is also determined by the probability of their overlap, and when receiving pulsed signals, it can be much higher.

Design and first performance results of waveform sampling readout electronics for Large Area Picosecond Photodetector

Large Area Picosecond Photodetectors (LAPPD) are a new generation of microchannel plate photomultipliers being manufactured by Incom. These devices feature large sensitive area of 350 cm2, high quantum efficiency (∼ 20%), and tens of picosecond single photon timing resolution. LAPPDs use an anode structure with 28 striplines, allowing for spatial resolution of 1 ÷ 3 mm while minimizing the number of readout channels. In this report, we present our design of integrated readout electronics for the LAPPD . These electronics read out all 2×28 channels of a stripline-anode LAPPD . Waveform sampling at up to 5GSPS is performed by 8 DRS4 switched-capacitor array ASICs. All DRS4 channels are digitized in parallel with two 32-channel ADCs. An on-board FPGA coordinates digitization and readout of waveforms, and could further be expanded to include some waveform processing. Data packages built in the FPGA are sent to a data acquisition system (DAQ) via optical fiber, with a baseline Gigabit Ethernet interface implemented entirely on the FPGA . The electronics is designed to accommodate different triggering options: self-triggering using DRS4 transparent mode and external triggering, making event control very flexible. Further flexibility is enhanced with embedded software for an on-FPGA soft-core processor, as well as DAQ readout and control software. The device is plug and play with any existing IP network. An open-source ecosystem is being developed to provide full control of the device operation and an easy way to integrate it to any environment. In the report we describe the status of the electronics development, its firmware and readout software. Also the results of the first tests of the electronics with the LAPPD devices will be presented.

Design of 1Gsps high-speed data acquisition card

In order to digitize the High-Frequency signal, a 12-bit 1Gsps RF Sampling data acquisition system is designed. The digital acquisition system includes an Analog-to-Digital Converter (ADC) daughter card and a data processing mother card equipped with Field Programmable Gate Arrays (FPGA) for communication, which has an external DDR3 memory module and a Gigabit Ethernet Interface. It focuses on the hardware system implementation of the daughter card and the realization of data receiving, transferring, and sending based on the FPGA. The test results show that the Effective Number of Bit (ENOB) of the acquisition card is above 9.1 Bits. Both Integral Non-Linear (INL) and Differential Non-Linearity (DNL) are anticipated. It accomplishes the requirements for engineering applications in many fields excellently.

Design and Performance of Data Acquisition and Control System for the Muon g-2 Laser Calibration

The Muon g-2 Experiment at Fermilab (E989) will measure the muon magnetic anomaly with unprecedented precision (0.14 ppm), which yields a factor of 4 improvement with respect to the previous measurements at Brookhaven National Laboratory (BNL) (E821). To achieve this goal, the relative response of each calorimeter channel must be calibrated and monitored at a level better than $10^{-3}$ in the time window of the muon fill. The calibration system uses a laser source and photodetectors. The data acquisition (DAQ) of the system is designed around two field-programmable gate array (FPGA)-based boards and a custom crate bus. The front-end board manages the photodetector operation and signal processing and performs a first-level data concentration task. Up to 12 FPGA boards can be housed in a 6U crate. A readout master controls the boards, implements event-building functionalities, manages the monitoring interface, and facilitates calibration and debugging tasks. A gigabit-ethernet interface is used to transfer data to the on-line farm for storage and further processing. Presently, the system is working at Fermi National Accelerator Laboratory (FNAL). In this article, we present the DAQ system design, run control user interface, and system evaluation.

Ethernet Embedded Readout Interface for Timepix2—Katherine readout for Timepix2

This paper introduces a readout system for the Timepix2. Firstly, this chip is described and the readout modes are discussed in detail. The new readout system presented is based on the Gigabit Ethernet interface and implements pre-processing, i.e. decoding of the raw pixel data, directly in the hardware. The device suppresses zero pixels, so that only useful data are sent to the computer/server. In a special independent mode, the readout can send completed data files to a remote server via SSH and does not need to use a control software. In island mode, the device stores measured data to a local storage (SD card). The process of calibration and its results are also discussed. An energy resolution of approximately 1.5 keV was achieved for 60 keV gamma-rays from an 241Am source. We present enhanced features of the readout system facilitating measurements and data evaluation, such as the HW support of clustering and Matrix Occupation Control. The former implements the pixel clustering directly in the hardware and sends energy calibrated results of the cluster finding algorithm to the computer. The latter automatically controls acquisition time of detector in order to reduce cluster overlapping. Measurements with Timepix2 are presented in iron and electron test beams. Results show that pixels of Timepix2 saturate at a per-pixel energy deposition of 1.9 MeV.

A New Method for Format Preserving Encryption in High-Data Rate Communications

In some encryption systems it is necessary to preserve the format and length of the encrypted data. This kind of encryption is called FPE (Format Preserving Encryption). Currently, only two AES (Advanced Encryption Standard) modes of operation recommended by the NIST (National Institute of Standards and Technology) are able to implement FPE algorithms, FF1 and FF3. These modes work in an electronic codebook fashion and can be configured to encrypt databases with an arbitrary format and length. However, there are no stream cipher proposals able to implement FPE encryption for high data rate information flows. The main novelty of this work is a new block cipher operation mode proposal to implement an FPE algorithm in a stream cipher fashion. It has been called CTR-MOD and it is based on a standard block cipher working in CTR (Counter) mode and a modulo operation. The confidentiality of this mode is analyzed in terms of its IND- CPA (Indistinguishability under Chosen Plaintext Attack) advantage of any adversary attacking it. Moreover, the encryption scheme has been implemented on an FPGA (Field Programmable Gate Array) and has been integrated in a Gigabit Ethernet interface to test an encrypted optical link with a real high data rate traffic flow.

Self-Synchronized Encryption for Physical Layer in Gigabit Ethernet Optical Links

In this work a new self-synchronized symmetric encryption solution for high speed communication systems necessary to preserve the format of the plaintext is proposed, developed and tested. This new encryption mechanism is based on the block cipher operation mode called PSCFB (Pipelined Statistical Cipher Feedback) and the modulo operation. The confidentiality of this mode is analyzed in terms of its IND-CPA (Indistinguishability under Chosen-Plaintext Attack) advantage, concluding that it can be considered secure in the same way as traditional modes are. The encryption system has been integrated in the physical layer of a 1000Base-X Gigabit Ethernet Interface, where the 8b/10b symbol flow is encrypted at line rate. Moreover, an implementation of the proposed system has been carried out in an FPGA (Field Programmable Gate Array) device. Finally, an encrypted optical link has been tested with real Ethernet frames, getting maximum throughput and protecting the data traffic from passive eavesdroppers.

Real-Time FPGA-Based Digital Signal Processing and Correction for a Small Animal PET

Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging, which requires high position and energy precision, as well as good flexibility and efficiency of the electronics. This paper presents the design of a digital signal processing logic for a marmoset brain PET system based on LYSO crystal arrays, SiPMs, and the resistive network readout method. We implement 32-channel signal processing in a single Xilinx Artix-7 Field-Programmable Gate Array (FPGA). The logic is designed to support four online modes which are regular data processing mode, flood map construction mode, energy spectrum construction mode, and raw data mode. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal locating, events filtering, and synchronization detection. Furthermore, a series of online corrections is also integrated, such as photon peak correction to 511 keV and time measurement result correction with crystal granularity. A Gigabit Ethernet interface is utilized for data transfer, Look-Up Tables (LUTs) configuration, and command issuing. The pipeline logic works at 125 MHz with a signal processing capability beyond the required data rate of 1,000,000 events/s/channel. A series of initial tests are conducted. The results indicate that the logic design meets the application requirement.

An Embedded System Processor Module with PCI Bus and Universal Communication Interface Based on PowerPC

In the high level applications of embedded systems such as Internet and data communication, the processor is an indispensable core module as the center of communication and control. An embedded system processor module with PCI bus and universal communication interface based on PowerPC is proposed in this paper. The central processor uses the Freescale PowerPC family of superscalar microprocessors with processing power of up to 733MIPS@400MHz. The microprocessor and peripheral conversion uses a bridge/memory controller that is seamlessly connected via a 60x bus. Regular large-capacity storage units such as SRAM, SDRAM, flash, and boot ROM are supported. Universal communication interfaces such as PCI bus interface, I2C bus interface, dual UART interface (RS485 level + RS232 level), Gigabit Ethernet interface, etc. are provided. The processor module has the characteristics of strong processor computing capability, common external interface and wide application, and could be directly used by developers, so that could shorten the development cycle.

Timepix3 detector network at ATLAS experiment

We describe the technical design and show results of first measurements of a network based on the Timepix3 and the Katherine readout (with Gigabit Ethernet interface) installed in the ATLAS cavern in the LHC in January 2018. The network consists of four Timepix3 detectors, arranged in two two-layer telescopes. All detectors in the network are synchronized with each other and the LHC orbit clock. The technical solution and the concept of the project are described in details. Since the radiation field inside ATLAS is rather harsh, only the detector units (sensors with power supplies) of the system are placed in the cavern. The detectors are connected to the readout electronics (situated in a rack room with radiation levels comparable to the natural background radiation) by 80 m long cables. The technical design was tested for distances up to 120 m. First measurements are presented, which demonstrate the capabilities of the ATLAS-TPX3 network.

Particle telescope with Timepix3 pixel detectors

In the presented work, we demonstrate how Timepix3 detectors, featuring the Katherine (Gigabit Ethernet interface) readout, can be used in a particle telescope. For the highly precise timestamp synchronization, a special timing unit (with time resolution ∼ 13 ps) based on a Time-to-Digital-Converter (TDC) is used and interconnected with the readouts. The designed concept of the measurement chain was tested at the SPS facilities at CERN in a 40 GeV/c pion beam using a telescope of 3 synchronized Timepix3 detectors. Evaluating spatially and temporally coincident events, an overall time resolution below 2 ns was determined, whereby a systematic error of <1 ns was present.

Katherine: Ethernet Embedded Readout Interface for Timepix3

The Timepix3—the latest generation of hybrid particle pixel detectors of Medipix family—yields a lot of new possibilities, i.e. a high hit-rate, a time resolution of 1.56 ns, event data-driven readout mode, and the capability of measuring the Time-over-Threshold (ToT - energy) and the Time-of-Arrival (ToA) simultaneously. This paper introduces a newly developed readout device for the Timepix3, called "Katherine", featuring a Gigabit Ethernet interface. The primary benefit of the Katherine is the operation of Timepix3 at long distance (up to 100 m) from computer or server, which is advantageous for the installation at beam lines, where the access is difficult or where radiation levels are too high for human interventions. The maximal hit-rate is limited by the bandwidth of the Ethernet connection (peer-to-peer connection; up to 16 Mhit/s). Since the Katherine interface is equipped with a processor of high computational power (ARM Cortex-A9 dual-core processor), it permits the use as a stand-alone (autonomous) radiation detector. The key features of the device are described in detail. These are the implemented high voltage power supply offering both polarities of bias voltage (up to ± 300 V), the automatic data sending to a sever via SSH, the automatic compensation of ToA values from columns with shifted matrix clock, etc. A dedicated control software was developed, which can be used for the detector preparation (sensor equalization, the DACs dependency scan, and the THL scan) and measurement control. Measured energy spectra from photon fields are shown.

Application of Signal Processing in GPS Signal Detection Using USRP

The Universal Software Radio Peripheral (USRP) is slowly becoming a very popular piece of hardware used in different universities and research labs across the world. It is inexpensive, which attracts a lot of attention, along with its variety of applications and capabilities. The USRP connects to a host-computer through a high-speed USB or Gigabit Ethernet interface. Another reason for the increasing popularity of the USRP is its ability to respond to multiple programming software such as GNU Radio, Matlab/Simulink, and LabView. There is a broad range of capabilities of the USRP one of which includes receiving GPS signals. Each GPS satellite transmits data on two frequencies, L1 (1575.42 MHz) and L2 (1227.60 MHz). We focused on the L1 band that transmits at 1575.42 MHz. The main objective was to engage in signal analysis with the carrier signal of the L1 band. This task proved to be challenging but not impossible. The carrier signal is essentially to carry information modulated on to it; in this case the navigation message from the GPS satellite along with other codes that are irrelevant to use at this point. After receiving the signal via USRP and with a simple extraction of the carrier signal, we were able to record the signal and reconstruct it using its In-phase and Quadrature phase (IQ) data. With just the carrier signal, one is able to do multiple things. One can modulate his/her own information onto the signal and transmit it through the USRP. Further analysis on the characteristics of the signal can be done. For example, one can compare the strength of a direct to the indirect signal. In theory, one can determine the characteristics of the surrounding area when comparing direct and indirect carrier signal. The possibilities are endless.

SPIDR, a general-purpose readout system for pixel ASICs

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a “soft core” CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

A Feasible Architecture for ARM-Based Microserver Systems Considering Energy Efficiency

In this paper, we propose the architecture of the ARM-based server system and physically build the ARM-based server cluster board (SCB). Based on a real implementation, the efficiency of the microserver is evaluated to verify the benefits of the proposed scheme. In experiments, every SCB is equipped with four server-grade ARM quad-core processors for enterprise-class applications. The major difference between our work and other studies is that this paper tests the performance of the server-grade processors, whereas previous works use the cluster system formed by the embedded processors. The experiment results show that the SCB-based systems perform with lower power-consumption than the x86 systems. Since various types of cluster systems can be built with the SCB through either the PCI Express (PCIe) interface or gigabit Ethernet interface, the proposed design of the ARM server board and the systems can, therefore, be extensively applied. This physical implementation and measurement show that the proposed architecture can work well. The proposed energy-saving (i.e., green) server designs with low-power processors are suitable for relative applications in the coming era of Industry 4.0 and the Internet of Things.

ADC evaluation boards design and test framework for LCLS-II precision receiver

In the low-level RF control field, ADC acquisition accuracy and noise set the boundary of our control ability, making it important to develop low-noise acquisition systems. From the design to test stage, all the noise terms should be understood and characterized. The specific need addressed here is the precision acquisition system for the second Linac Coherent Light Source (LCLS-II), led by SLAC National Accelerator Laboratory. Test circuit boards for the LTC2174 and AD9268 ADCs are designed and fabricated by LBNL. An ADC test framework based on FPGA evaluation board to assess performance has been developed. The ADC test framework includes both DSP (Digital Signal Processing) firmware and processing software. It is useful for low-level RF control and other synchronization projects. Investigating the clock jitter between two channels give us an understanding of that noise source. Working with the test framework, the raw ADC data are transferred to a computer through a Gigabit Ethernet interface. Then short-term error signal can be calculated based on a sine wave fit. By changing low-pass filter bandwidth, relative long-term performance can also be obtained. Amplitude jitter and differential phase jitter are the key issues for ADCs. This paper will report the test results for LTC2174 and AD9268 chips. The integral amplitude jitter is smaller than 0.003 %, and the integral phase noise is smaller than $$0.0015^{\circ }$$ (measured at 47 MHz RF, 100 MHz clock, bandwidth 1 Hz to 100 kHz) for both ADC chips.

A synchronous Gigabit Ethernet protocol stack for high-throughput UDP/IP applications

State of the art detector readout electronics require high-throughput data acquisition (DAQ) systems. In many applications, e. g. for medical imaging, the front-end electronics are set up as separate modules in a distributed DAQ. A standardized interface between the modules and a central data unit is essential. The requirements on such an interface are varied, but demand almost always a high throughput of data. Beyond this challenge, a Gigabit Ethernet interface is predestined for the broad requirements of Systems-on-a-Chip (SoC) up to large-scale DAQ systems. We have implemented an embedded protocol stack for a Field Programmable Gate Array (FPGA) capable of high-throughput data transmission and clock synchronization. A versatile stack architecture for the User Datagram Protocol (UDP) and Internet Control Message Protocol (ICMP) over Internet Protocol (IP) such as Address Resolution Protocol (ARP) as well as Precision Time Protocol (PTP) is presented. With a point-to-point connection to a host in a MicroTCA system we achieved the theoretical maximum data throughput limited by UDP both for 1000BASE-T and 1000BASE-KX links. Furthermore, we show that the random jitter of a synchronous clock over a 1000BASE-T link for a PTP application is below 60 ps.

Gigabit Ethernet signal transmission using asynchronous optical code division multiple access.

We propose and experimentally demonstrate a novel architecture for interfacing and transmitting a Gigabit Ethernet (GbE) signal using asynchronous incoherent optical code division multiple access (OCDMA). This is the first such asynchronous incoherent OCDMA system carrying GbE data being demonstrated to be working among multi-users where each user is operating with an independent clock/data rate and is granted random access to the network. Three major components, the GbE interface, the OCDMA transmitter, and the OCDMA receiver are discussed in detail. The performance of the system is studied and characterized through measuring eye diagrams, bit-error rate and packet loss rate in real-time file transfer. Our Letter also addresses the near-far problem and realizes asynchronous transmission and detection of signal.

Embedded Linux platform for data acquisition systems

This scalable hardware–software system is designed and developed to explore the emerging open standards for data acquisition requirement of Tokamak experiments. To address the future need for a scalable data acquisition and control system for fusion experiments, we have explored the capability of software platform using Open Source Embedded Linux Operating System on a programmable hardware platform such as FPGA. The idea was to identify the platform which can be customizable, flexible and scalable to support the data acquisition system requirements. To do this, we have selected FPGA based reconfigurable and scalable hardware platform to design the system with Embedded Linux based operating system for flexibility in software development and Gigabit Ethernet interface for high speed data transactions. The proposed hardware–software platform using FPGA and Embedded Linux OS offers a single chip solution with processor, peripherals such ADC interface controller, Gigabit Ethernet controller, memory controller amongst other peripherals. The Embedded Linux platform for data acquisition is implemented and tested on a Virtex-5 FXT FPGA ML507 which has PowerPC 440 (PPC440) [2] hard block on FPGA. For this work, we have used the Linux Kernel version 2.6.34 with BSP support for the ML507 platform. It is downloaded from the Xilinx [1] GIT server. Cross-compiler tool chain is created using the Buildroot scripts. The Linux Kernel and Root File System are configured and compiled using the cross-tools to support the hardware platform. The Analog to Digital Converter (ADC) IO module is designed and interfaced with the ML507 through Xilinx Generic Interface (XGI) expansion headers. The Custom IP Core is designed and implemented in FPGA to interface the external ADC with DMA engine of the on-chip processor block. The data acquisition from ADC interface is successfully achieved and the captured data is sent to the host PC on mounted NFS share (Network File System) through LAN (Local Area Network). The detailed hardware and software design, development and testing results will be discussed in the paper.

Towards Software-Based Real-Time Singles and Coincidence Processing of Digital PET Detector Raw Data

This paper presents a software-based singles and coincidence processing (SCP) architecture for a digital PET/MR system that is based on SiPM detectors with local digitization coupled to preclinical crystal arrays. Compared with traditional PET systems, our system outputs detector raw data of the individual detector elements via optical Gigabit Ethernet interfaces instead of singles or coincidences. The raw data contains the digitized timestamps, energies, and identifiers of triggered SiPM pixels (hits). Although this approach requires a high bandwidth for the detector data transmission system, the availability of detector raw data offers unique opportunities to employ more accurate and computationally complex, iterative algorithms, which can lead to PET images with higher quality and accuracy. In this paper, we evaluate a parallel software-based SCP for three different crystal position estimation approaches with regard to its real-time capabilities. The SCP receives detector raw data as input and outputs list-mode coincidence data. The investigated PET system features ten singles processing units (SPU), each equipped with two PET detector stacks and a Gigabit Ethernet interface to a data acquisition and processing server (Dell Poweredge R910 equipped with 4× Intel Xeon X7560@2.27 GHz CPUs and 256 GByte DDR3-RAM), allowing lossless real-time acquisition of the entire raw data stream. Using the detector raw data of three previously stored measurements, our results show that the throughput (in Mhits/s) of a center-of-gravity (COG)-based parallel SCP is nearly 4× higher on average than the estimated detector raw data output that is generated from an activity of 37 MBq in the iso-center of the detector ring. Under the same conditions, an iterative maximum-likelihood (ML)-based parallel SCP leads to a 6× higher throughput on average, while a Gaussian-based parallel SCP also results in a 13× higher throughput on average. Compared with a serial processing approach, the parallel implementations show speedups of up to 38× on average for the ML-based, 39× on average for Gaussian-based, and up to 34× on average for the COG-based parallelized SCP for the three previously-stored measurements.