Gbit DRAM Research Articles

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Aiming to resolve memory bottlenecks in multi-core system, novel 1-Tbyte/s 1-Gbit DRAM architecture based on a multi-core configuration and 3-D interconnects was developed. The DRAM stacked on a multi-core CPU has 512-bit I/Os with through-silicon-via (TSV) distributed in 16 memory cores. Five-stage pipelined architecture in the compact DRAM core was developed to reduce the operation cycle of the data-bus to 2 ns. A low-noise early-bar-write scheme for an 8-ns cycle array operation and 16-Gbit/s I/O circuits on TSV were also developed. The proposed DRAM architecture greatly improves power efficiency. TSV scheme reduces the parasitic capacitance of the interconnects between the DRAM and CPU, and multi-core architecture reduces the length of the data bus on the DRAM. A 1-Gbit DRAM was designed based on the 45-nm stand-alone DRAM process. Chip size is 51.6 mm2 assuming 4F2 memory cells, and the density is about 5 times higher than that of embedded DRAM. Circuit simulations confirmed the 2-ns operation of the data bus, 8-ns operation of the memory array, and 16-Gbit/s operation of I/O circuits. Power consumption is 19.5 W, providing power efficiency of 51.3 Gbyte/s/W, which is an order of magnitude higher than that of conventional DRAMs.

0.5-V Low-$V _{\rm T}$ CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

A novel low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of a sense amplifier (SA) with the proposed preamplifier and its activation schemes at a data-line voltage of 0.5 V was 6 ns, which is 62% shorter than that of an SA using a conventional preamplifier. By activating the proposed preamplifier temporarily during the write cycle, the writing time was 16.3 ns, which is 72% shorter than the case without activation of the proposed preamplifier, and this time is short enough to apply a DRAM array using the proposed preamplifier to 1.6-Gbit/s/pin DDR3 SDRAM. The operating current of the memory array and its peripheral circuit including the proposed preamplifier was reduced by 12% by reducing the data-line voltage from 0.8 to 0.5 V.

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection and a cyclic redundancy check (CRC) generator for outer-data inner-command architecture. Measurements for bit error rate and jitter performance of the transmitter was performed on an electrical test board which emulates the real memory system's environment. Also, the effect on power noise was analyzed from the DRAM chips with three class values of power decoupling capacitance for the peripheral part. The results show that no additional coding for the differential I/O protection in DRAM, like CRC, is required up to 5.8-Gb/s/pin operation.

DRAM retention tail improvement by trap passivation

A very efficient method to reduce gate induced drain leakage (GIDL) as the dominant leakage path in the tail part of DRAM data retention time distribution is presented. Different to other reports, GIDL is addressed by trap passivation instead of lowering of electric fields. Stable passivation of traps is achieved by implantation of fluorine into S/D regions of 512 Mbit and 1 Gbit DRAMs in 110 nm technology. It was found that the position of the F-implant within the process flow plays a key role to enable trap reduction and retention tail improvement. Systematic implant experiments were carried out resulting in a failcount reduction of up to 40%. Detailed activation energy analysis on individual memory cells confirms the validity of the retention tail model and the selective reduction of GIDL traps by F-implantation.

A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

Development of 3D-Packaging Process Technology for Stacked Memory Chips

ABSTRACTA 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.

Novel Storage-Node Contacts with Stacked Point-Cusp Magnetron Sp-TiN Barrier for Metal–Insulator–Metal Ru/Ta2O5/Ru Capacitors in Gigabit Dynamic Random Access Memories

We have investigated a mechanism for increasing the contact resistance (Rc) of the ruthenium (Ru) and the titanium nitride (TiN) barrier during the tantalum oxide (Ta2O5) oxidation annealing in the metal–insulator–metal (MIM) capacitors. It has been found that controlling the atomic ratio of Ti to N (Ti/N ratio) is a key to keeping the contact resistance low. Controlling the Ti/N ratio is easy for the sp-TiN, while it is difficult for the chemical-vapor-deposited TiN. On the basis of this result, we have proposed a novel Ru/TiN contact with a stacked-barrier structure fabricated by using the point-cusp magnetron (PCM) sputtering method. We have applied this structure to the MIM-Ru/Ta2O5/Ru capacitor in a gigabit DRAM with 0.10 µm design. In this capacitor, we have obtained the contact resistance of 10 kΩ·bit and the capacitor leakage current of 10-17 A/bit in the range of -1 to +1 V.

Two-phase boosted voltage generator for low-voltage drams

A two-phase boosted voltage (V/sub PP/) generator circuit was proposed for use in gigabit DRAMs. It reduced the maximum gate-oxide voltage of pass transistor and the lower limit of supply voltage to V/sub PP/ and V/sub TN/, respectively, while those for the conventional charge-pump circuit are V/sub PP/+V/sub DD/ and 1.5 V/sub TN/ respectively. Also, the pumping current was increased in the new circuit. The newly proposed two-phase V/sub PP/ charge-pump circuit worked successfully at V/sub DD/ down to 0.8 V by eliminating the threshold voltage loss of the control pulse generator and was tested successfully in a 0.16-/spl mu/m test chip using triple-well CMOS technology.

An Electronics Division Retrospective (1952-2002) and Future Opportunities in the Twenty-First Century

The emergence of crystalline silicon and silicon-based materials such as silicon-germanium as the premier materials and the personnel driving the integrated circuit (IC) microelectronics revolution will be reviewed. The major threshold events from the 1940s through the mid-1960s, presaging the onset of the large scale integration microelectronics era, will be highlighted. The major silicon material challenges such as dislocation-free single-crystal growth, plastic deformation, the point-defect dilemma, gettering, oxygen in silicon, carrier lifetime, and controlled point-defects in the silicon crystal during the evolution of silicon microelectronics from large scale integration through the very large scale integration era in the 1970s and the 1980s into the ultralarge scale integration era of the 1990s will then be reviewed. Opportunities in epitaxy, wafer cleaning, silicon-on-insulator, silicon-germanium, IC scaling and potential changes in device configuration and IC architecture in the evolution towards the 64 Gbit DRAM and 9 G transistor high-performance MPU logic era in 2016 (per the 2001 edition of the International Technology Roadmap for Semiconductors) will be discussed in the context of silicon-based microelectronics. The complementary role of compound semiconductors, nanoelectronics and the continuing initiative to obtain an optoelectronic system compatible with silicon will also be discussed. Finally, nonsilicon materials and device configurations will briefly be noted. © 2002 The Electrochemical Society. All rights reserved.

TiN barriers for high-k capacitors: simulations and experimental results

High k dielectric materials have drawn a lot of attention for gate dielectric applications as substitutes for SiO 2 in future ULSI devices and storage capacitors in GBit DRAMs. Tunneling currents become a major problem with shrinking device geometries. Capacitor stacks with high k dielectrics like BST or Ta 2O 5 will need barriers like TiN to avoid intermixing between poly-Si and electrode material. A new clusterable RTCVD module for TiN deposition using TiCl 4 and NH 3 chemistry was developed and built up by STEAG RTP Systems GmbH. The design of the reactor was strongly supported by simulations and methods of experimental design. Simulations on the behaviour of TiCl 4 and NH 3 process gas flows during process conditions in the RTCVD reactor chamber using Lennard Jones Potential approximation and Phoenics CVD software show that the two main gas species TiCl 4 and NH 3 behave very different and thus thoroughly have to be treated individually. We demonstrated and discussed gas flow homogeneity distributions of different reactor designs and constraints and show how the obtained results led us to the chamber design, which finally was realized. Experimental cross checks on TiN deposited wafers processed with our new RTCVD reactor for TiN barrier are shown and the results are discussed in detail.

Three dimensional (BA, SR) TIO3 stack capacitors for dram application

Three dimensional integration of BSTO thin films for Gigabit DRAM application is performed by a MOCVD BST process combined with a high temperature barrier stack of TaSiN/Ir/IrO2 with SiO2 sidewall protection. The SiO2 layer is formed by a new low temperature HDP process. This barrier stack enables the use of a new two step high temperature MOCVD BST process, which results in high quality BST films. First, a very thin BST seed layer is deposited at 450°C. The second layer is formed at 640°C. Using these two key processes, we have established a baseline for BST capacitors on 0.2μm feature size. 256k capacitor arrays show capacitance up to 18.1 fF/cell with excellent leakage current around 1 fA/cell (DC, 1V). The capacitance is scaling with different capacitor arrays (4k to 256k).

The impacts of SILC and hot carrier induced drain leakage current on the refresh time in DRAM

This paper reports the temperature dependence of SILC and hot carrier induced drain leakage current, and their impact on the refresh time in Giga-bit level DRAM with practical considerations. SILC has been found to increase as the monitoring and stress temperature increases. Due to the generation of interface states, hot carrier induced pn junction leakage current and band-to-band tunneling current have been found to increase as the monitoring temperature increases.From the simulation results of a refresh circuit for Giga-bit level DRAM, it has been found that the increase of SILC with stress time is a dominant factor in refresh failure below 373K, and the pn junction leakage current will be a dominant factor at the high elevated temperature. It has been also observed that the increase of hot carrier induced drain leakage current can be a cause for the refresh failure.

A novel low-temperature (Ba,Sr)TiO 3 (BST) process with [formula omitted] barrier for Gbit DRAM applications

A new, low temperature (Ba,Sr)TiO 3 (BST) MOCVD process has been established at 580°C deposition temperature which can be used for Gbit DRAM applications using Ti TiN as barrier material. The process window for BST deposition was investigated in terms of deposition temperature, stoichiometry, film thickness, post annealing treatment and variation of the underlying electrode/barrier layer. Electrical characterization revealed specific capacitance values of 45 fF/μm 2 for 25 –30 nm film thickness and 75 fF/μm 2 for 10 nm film thickness which is close to the target value for GBit of 80 – 100 fF/μm 2. Oxidation resistance of the Ti TiN barrier could be shown up to 600°C. Feasibility of this low temperature BST process has been successfully demonstrated using a 4 Mbit test vehicle.

Multiple twisted dataline techniques for multigigabit DRAMs

To provide reliable scaled DRAMs, new multiple twisted dataline techniques are proposed and analyzed. Their effectiveness in reducing both the bitline (BL) and wordline (WL) coupling noises in scaled DRAM's was evaluated by means of soft-error-rate measurements on 256-Mbit and 1-Gbit DRAM test chips. At the 1-Gbit level of integration, in our proposed scheme-compared to the conventional twisted bitline (TBL) scheme-the chip area penalty due to twisting is reduced by 66% and the BL coupling noise is reduced by 45%. At the 256-Mbit level, when the proposed technique is applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional TBL and WL schemes. Faster data access time can also be expected when the proposed technique is applied to BL and/or WL structures.

Process and characterization of (Pb,La)TiO3 thin films deposited by MOCVD for gigabit DRAM application

La-modified lead titanate. (Pb. La)TiO 3 . [PLT], thin films were deposited by low pressure metal organic chemical vapor deposition (MOCVD) on Pt/SiO2/Si substrates. The composition of the films was studied with various deposition conditions. Also, the electncal properties, such as the diclectric constant, the P-E hysteresis curve, and the leakage current density, were investigated with various annealing conditions The experimental results show that the 180nm-thick PLT films with the La mole % of 12 are applicable as the planar capacitor layer of I gigabit DRAM.

Technology challenges and solutions for 1Gbit and beyond

The need for higher DRAM densities, for cost effective manufacturing and the price pressure puts the DRAM development on a highly innovative path. The fast pace with which DRAM cell sizes are reduced results in many technology issues. This talk discusses the deep trench cell architecture, its advantages and the main technology innovations that have made the aggressive scaling of the DRAM cell possible. The issues related to Gbit DRAMs, the new challenges and potential innovations will be presented.

IS PHYSICALLY SOUND AND PREDICTIVE MODELING OF NMOS SUBSTRATE CURRENTS POSSIBLE?

Practically all NMOS substrate current models used today, which have been successfully verified for a certain range of NMOS devices and bias conditions, yield for a given homogeneous electric field an impact ionization coefficient which is significantly smaller than the corresponding experimental result extracted from bulk silicon. This effect was named “surface impact ionization”, but no conclusive physical explanation was given for this discrepancy. This obvious inconsistency has led to serious doubts concerning the predictive capabilities of these substrate current models, and in fact none of these models could be verified over the full range of available NMOS technologies. However, recently two different substrate current models, (a full-band Monte Carlo model and a nonlocal soft-threshold lucky electron model) appeared, which are consistent with bulk impact ionization and provide accurate substrate current results for advanced NMOS devices without any modification of the model parameters. In this paper we have demonstrated that these models are precise for several NMOS devices fabricated in very different technologies covering the range from the 256 KBit to 1 GBit DRAM generation. To the best of our knowledge this is the widest technology base used for verification so far, which implies that these two models are the first models which really deserve to be called predictive. On the other hand, it is shown that the two substrate current models used most frequently today have poor modeling accuracy and cannot be called predictive at all. Finally, previous work concerning surface impact ionization is re-investigated with full-band Monte Carlo in the light of the new findings. It is shown that the effect called surface impact ionization cannot be associated with an effect in microscopic physics, but is due to the failure of the impact ionization models which have been applied to extract the impact ionization coefficient by reverse engineering based on experimental NMOS substrate currents. In addition the few theoretical explanations of surface impact ionization are discussed and the proposed effects are shown to be of minor influence.

Micro-Processing by ArF Excimer Laser

KrF/ ArF excimer laser lithography technique are expected to realize 1-4 Gbit DRAMs below 0.25μm designrules. Although KrF lithography is extendable for less than 0.2 μm patterning, the introduction of ArF lithography is much simple solution, if the infrastructures of ArF lithography are available. To realize ArFlithography in mass production, the development of ArF resists, exposure tools, and masks are important.Regarding ArF resists, practical chemically amplified resist has been developed with alicyclic polymers. Thedevelopment of dry-developed processes using silylation techniques also improves the resolution. Thecombination of recent ArF resist, anti-reflecting coating and attenuating phase shifting mask can producedevice patterns with a 0.12 μm design rule. The use of TSI can produce 0.09μm Line & Space (L&S) patternswith Levenson phase shift mask. These results imply that ArF lithography can be used for multi-generation indevice manufacturing. ArF lithography will be introduced in mass production as post-KrF lithography in thenear future.

Two-phase back-bias generator for low-voltage gigabit DRAMs

A two-phase back-bias (VBB) generator is proposed for use in gigabit DRAMs using triple-well CMOS technology. The lower limit of VCC for the proposed VBB generator is a single VT (threshold voltage), whereas that for the conventional VBB generator is 2·VT.

Improved Alignment Accuracy Using Lens-Distortion Correction for Electron-Beam Lithography in Mix-and-Match with an Optical Stepper

The mix-and-match use of an electron-beam (EB) lithography system and an optical stepper is an effective approach to achieving higher resolution while maintaining high throughput in the fabrication of Gbit DRAMs and advanced ASIC devices. In this approach, the highly accurate alignment of patterns exposed by different lithography methods is essential. In this paper, the lens distortion of the optical stepper is examined and distorted patterns are aligned with an EB lithography system. The overlay accuracy in this mix-and-match application was 51.4 nm (3σ) which corresponds to Gbit DRAMs fabrication.