Abstract
A two-phase boosted voltage (V/sub PP/) generator circuit was proposed for use in gigabit DRAMs. It reduced the maximum gate-oxide voltage of pass transistor and the lower limit of supply voltage to V/sub PP/ and V/sub TN/, respectively, while those for the conventional charge-pump circuit are V/sub PP/+V/sub DD/ and 1.5 V/sub TN/ respectively. Also, the pumping current was increased in the new circuit. The newly proposed two-phase V/sub PP/ charge-pump circuit worked successfully at V/sub DD/ down to 0.8 V by eliminating the threshold voltage loss of the control pulse generator and was tested successfully in a 0.16-/spl mu/m test chip using triple-well CMOS technology.
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