Gigascale Systems Research Center Research Articles

Multi-objective Floorplanning optimization engaging dynamic programming for system on chip

The quest for optimal VLSI Floorplanning (FP) addressing noteworthy challenges namely Area, Wirelength, and Temperature remains an ongoing field of research. Prevailing FP designs individually optimize these constraints that increase the model complexity with reduced efficiency. Given this motivation, this study provides an optimum FP aimed at minimizing the overall chip area by adhering to the standard design requirements. Accordingly, the divide-and-conquer model of Dynamic Programming (DP) adopted in this work simultaneously optimizes the chip area by devising separate analytical cost functions related to the physical design parameters that are then collated to yield the compact Floor plan. The formulated DP optimization coined as Weighted Aggregated DP-Based FP (WADPFP) adaptively tunes the cost function using rank-sum scaled weights and the discount factor thereby reducing congestion and hotspots. This objective is met using two novel recursive functions ensuring temperature and area scalability. Simulation and synthesis of the proposed FP on the Microelectronic Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) Benchmark circuits demonstrated the viability of the automated FP design by registering 6.05%, 13%, and 4.35% reduction in area, wirelength, and temperature respectively in comparison with the traditional and recent peers. Additional analysis on the AMI49_X benchmark circuits emphasizes the scalable nature of the introduced WADPFP.

Floorplanning for Area Optimization Using Parallel Particle Swarm Optimization and Sequence Pair

In the integrated circuit (IC) designing floorplanning is an important phase in the process of obtaining the layout of the circuit to be designed. The floorplanning determines the performance, size, yield, and reliability of VLSI ICs. The obtained results in this step are necessary for the other consecutive process of the chip designing. VLSI floorplanning from the computational point of view is a non-polynomial hard (NP-hard problem), and hence cannot be efficiently solved by the classical optimization techniques. In this paper, we have proposed a metaheuristic approach to address the problem by using the parallel particle swarm optimization (P-PSO) technique. The P-PSO uses a new greedy operation on the sequence pair (SP) to explore the search space to find an optimal solution. Experimental results on the Microelectronic Centre of North Carolina and Gigascale Systems Research Center benchmark shows that the applied parallel PSO (P-PSO) may be used to produce an optimal solution.

A nature inspired optimization algorithm for VLSI fixed-outline floorplanning

VLSI floorplan optimization problem aim to minimize the following measures such as, area, wirelength and dead space (unused space) between modules. This paper proposed a method for solving floorplan optimization problem using Genetic Algorithm which is named as ‘Lion Optimization Algorithm’ (LOA). LOA is developed for non-slicing floorplans having soft modules with fixed-outline constraint. Although a number of GAs are developed for solving VLSI floorplan optimization problems, they are using weighted sum approach with single objective optimization and crossover between two B*tree structure is not yet attempted. This paper explains, power of B*tree crossover operator for multiobjective floorplanning problem. This operator introduces additional perturbations in initial B*tree structure to create two new different B*tree structures compared with classical GA approach. Simulation results on Microelectronics Center of North Carolina and Gigascale Systems Research Center benchmarks indicate that LOA floorplanner achieves significant savings in wirelength and area minimization also produces better results for dead space minimization compared to previous floorplanners.

Planning Massive Interconnects in 3-D Chips

3-D chips rely on massive interconnect structures, i.e., large groups of through-silicon vias coalesced with large multibit buses. We observe that wirelength optimization, a classical technique for floorplanning, is not effective while planning massive interconnects. This is due to the interconnects’ strong impact on multiple design criteria like wirelength, routability, and temperature. To facilitate early design progress of massively-interconnected 3-D chips, we propose a novel 3-D-floorplanning methodology which accounts for different types of interconnects in a unified manner. One key idea is to align cores/blocks simultaneously within and across dies, thus increasing the likelihood of successfully implementing complex and massive interconnects. While planning such interconnects, we also target fast, yet accurate, thermal management, routability, and fixed-outline floorplanning. Experimental results on Gigascale Systems Research Center and IBM-HB+ circuits demonstrate our tool’s capabilities for both planning massive 3-D interconnects and for multiobjective 3-D floorplanning in general.

Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence

With the ever-increasing power demands of consumer electronics and portable devices, multi-supply voltage (MSV) technique is supposed as one of the direct and effective ways for power optimization in SoC designs. To realize MSV implementation, procedures such as voltage assignment, voltage island partitioning and level shifters (LSs) placement should be considered simultaneously during the floorplanning stage. Although many works addressed the MSV-driven design problem, few of them actually took account of LS placement, which makes the generated results may limit the potential applications. Furthermore, existing design frameworks are often very computationally expensive, and it is not beneficial to shorten the time to market. In this paper, we present an MSV-driven SoC floorplanning framework for fast design convergence. Several techniques are proposed and integrated into an efficient and flexible non-randomized floorplanning algorithm. Firstly, to reserve the desired deadspace for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. Secondly, a heuristic based voltage assignment method is presented for accuracy and execution time trade-off. Thirdly, different from previous works which do voltage assignment without physical information feedback, an inner loop is built between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 12%, CPU time by 48% with 4% area increase.

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

AbstractFrom the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time‐to‐market of the product. A new perturbation method, called Cull‐and‐Aggregate Bottom‐up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable‐order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two‐dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference‐based cost function (one‐dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near‐optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near‐optimal outcome as compared to the other existing algorithms. Copyright © 2013 John Wiley & Sons, Ltd.

Variable-Order Ant System for VLSI multiobjective floorplanning

Floorplanning is crucial in VLSI chip design as it determines the time-to-market and the quality of the product. In this work, Variable-Order Ant System (VOAS) is developed and combined with a floorplan model namely Corner List (CL) to optimize the area and wirelength. CL is used to represent the floorplan layout. Although CL has proven to have the same search space and time complexity as Corner Sequence (CS), comparatively, CL has more corners to be selected. This compensates the sequence weakness, where modules can be placed freely onto the corners, which are not bounded by the floorplan contour. Two groups of ants, namely VOAS and reconnaissance ants, which will collaborate with each other to determine the local information, are introduced. Through this cooperation, VOAS ant can ascertain its local information greedily, based on the local search space information carried out by reconnaissance ants. Subsequently, VOAS ant proposes a new variable-order property to prioritize the global and local explorations. The variable-order property enables the ants in VOAS to weigh a better choice of modules for the floorplanning, based on the local and global information. The update rules of VOAS are modified in order to handle two-dimensional problem, such as VLSI floorplanning. VOAS shows improved results in terms of purely area optimization as well as composite function of area and wirelength, as compared to other state-of-the-art and recent floorplanning/placement algorithms based on Microelectronics Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) benchmarks.

Hierarchical congregated ant system for bottom-up VLSI placements

A new perturbation method, called Hierarchical-Congregated Ant System (H-CAS) has been proposed to perform the variable-order bottom-up placement for VLSI. H-CAS exploits the concept of ant colonies, where each ant will generate the perturbation based on differences in dimensions of the VLSI modules in hard modules floorplanning and differences in area of the VLSI modules in soft modules floorplanning. In this paper, it is mathematically proved that the area-based two-dimensional cost function for hard modules floorplanning problem can be reduced to the difference-based one dimensional cost function which avoids local optima problems. Lack of global view is a major drawback in the conventional bottom-up hierarchy, and hence, ants in the H-CAS are made to introduce global information at every level of bottom-up hierarchy. A new relative whitespace formula for bottom-up hierarchy is derived mathematically and the H-CAS embeds it in its unique update formula. The ants in H-CAS are able to communicate among themselves and update the pheromone trails when they reach the destination. Then, the ants will congregate, share their experiences and construct a new pheromone trails that belong to this newly constructed group. The congregation of at least two ants and/or ant consortiums would lead to reduction in subsequent search space and complexity. H-CAS gives the best-so-far near optimal solutions and yields low standard deviations of areas involving 9–600 blocks based on Microelectronics Center of North Carolina (MCNC) and Giga scale Systems Research Center (GSRC) benchmarks. The results obtained establish that H-CAS is a high performance placer in respect of scaling, convergence, precision, stability, and reliability. The above claims are based on the comparisons with the other floorplanning algorithms as depicted graphically.

Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem

Modern very large scale integration technology is based on fixed-outline floorplan constraints, mostly with an objective of minimizing area and wirelength between the modules. The aim of this work is to minimize the unused area, that is, dead space in the floorplan, in addition to these objectives. In this work, a Simulated Annealing Algorithm (SAA) based heuristic, namely Simulated Spheroidizing Annealing Algorithm (SSAA) has been developed and improvements in the proposed heuristic algorithm is also suggested to improve its performance. Exploration capability of the proposed algorithm is due to the mechanism of reducing the uphill moves made during the initial stage of the algorithm, extended search at each temperature and the improved neighborhood search procedure. The proposed algorithm has been tested using two kinds of benchmarks: Microelectronics Center of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC). The performance of the proposed algorithm is compared with that of other stochastic algorithms reported in the literature and is found to be efficient in producing floorplans with very minimal dead space. The proposed SSAA algorithm is also found more efficient for problems of larger sizes.

The GSRC's Role in Meeting Tomorrow's Design Challenges

In the late 1990s, the US Office of the Secretary of Defense (OSD) established a joint research program with the Semiconductor Industry Association (SIA) through the Semiconductor Research Corp. (SRC), known as the Focus Center Research Program. One of these FCRP centers is the Gigascale Systems Research Center (GSRC), whose focus is on the systems architecture and design aspects of electronics technology. The research of the GSRC is of great value to the US Department of Defense, since design remains an important challenge for DoD systems. This partnership is an excellent example of government and industry collaboration on precompetitive research of common interest and benefit.

Not just research as usual

This issue of IEEE Design & Test focuses on one of the five centers within the Focus Center Research Program (FCRP), the Gigascale Systems Research Center, which addresses systems architecture and design aspects of electronics systems in the late- and post-silicon eras. Six articles written by the center researchers provide an overview of the visions and their key research results. This special issue also features a dynamic interview with Intel Chair Craig Barrett, who is generally considered to be the "father" of the FCRP. Finally, there is a general-interest article that reviews several chip-cooling techniques and presents an alternative approach based on a digital-microfluidic platform.

Guest Editors' Introduction: System IC Design Challenges beyond 32 nm

This special issue highlights ongoing research to address some of the challenges in the design of large ICs with dimensions well below 100 nm. The Gigascale Systems Research Center is organized around four themes and a design driver, and each is represented in this issue. There is also an exciting interview with Intel chair Craig Barrett. Accompanying the theme articles are three sidebars written by industry leaders (Richard Oehler of AMD, Ajith Amerasekera of Texas Instruments, and Leon Stok of IBM) on the challenges they see on the horizon, the paths being taken to address these challenges, and the role university programs can play. In addition, a Perspectives article by John Zolper discusses the value of this collaborative program to US national interests, including national security. Finally, there is a Last Byte column by the FCRP executive director Betsy Weitzman.

Challenges and Solutions for Late- and Post-Silicon Design

As technology scaling becomes more difficult, continuing advances in electronic products and their underlying ICs increasingly rely on innovative design solutions. This article outlines some of the complexity, reliability, and productivity challenges and how the Gigascale Systems Research Center is addressing them.

Reliable Systems on Unreliable Fabrics

The continued scaling of silicon fabrication technology has led to significant reliability concerns, which are quickly becoming a dominant design challenge. Design integrity is threatened by complexity challenges in the form of immense designs defying complete verification, and physical challenges such as silicon aging and soft errors, which impair correct system operation. The Gigascale Systems Research Center Resilient-System Design Team is addressing these key challenges through synergistic research thrusts, ranging from near-term reliability stress reduction techniques to methods for improving the quality of today's silicon, to longer-term technologies that can detect, recover, and repair faulty systems. These efforts are supported and complemented by an active fault-modeling research effort and a strong focus on functional-verification methodologies. The team's goal is to provide highly effective, low-cost solutions to ensure both correctness and reliability in future designs and technology nodes, thereby extending the lifetime of silicon fabrication technologies beyond what can be currently foreseen as profitable.

Variability and New Design Paradigms

In the late- and post-silicon eras, variation of all nanometer processes will continue to increase significantly. The industry is gradually addressing this situation and exposing more variability information to the designer. According to the Gigascale Systems Research Center, the deterministic era will be over for most on-chip applications and alternatives must be found. The author of this sidebar looks forward to the time when the two will meet: when more revolutionary design techniques will find their way into practical designs, and when one of the computational paradigms will suddenly be needed to cope with an unexpected surge in variability or reliability in a particular design or technology.

Fast floorplanning by look-ahead enabled recursive bipartitioning

A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by the explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called partitioning to optimize module arrangement (PATOMA), generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time. Experiments on standard Gigascale Systems Research Center benchmarks compare PATOMA to the Capo macro placer, the Traffic floorplanner, and to both the default and high-effort modes of the Parquet 4.0 floorplanner. With all blocks hard, PATOMA's average wirelength is comparable to the high-effort mode of Parquet 4.0 floorplanner and Capo, while PATOMA runs significantly faster. With all blocks soft, PATOMA produces wirelength 9% shorter on average than that of Parquet's default mode, and PATOMA runs seven times faster. For a new set of benchmarks with a mix of 500 to 2000 hard and soft blocks, PATOMA produces results with wirelengths roughly half of Parquet's, with a speedup of almost 200times

An orthogonal simulated annealing algorithm for large floorplanning problems

The conventional simulated annealing with some random generation mechanism using the sequence-pair topological representation in block placement and floorplanning is effective for a very small number of modules (40-50). This paper proposes an orthogonal simulated annealing algorithm (OSA) with an efficient generation mechanism (EGM) for solving large floorplanning problems. EGM samples a small number of representative floorplans and then efficiently derives a high-performance floorplan by using a systematic reasoning method for the next move of OSA based on orthogonal experimental design. Furthermore, an improved swap operation is proposed which cooperates with EGM to make OSA efficient. Excellent experimental results using the Microelectronics Center of North Carolina and the Gigascale Systems Research Center benchmarks show that OSA performs better than existing methods for large floorplanning problems.