GHz Ultra-wideband Low-noise Amplifier Research Articles

3‐5 GHz multifinger CMOS LNA using a simultaneous noise and impedance matching technique by a significant reduction of broadband impedance variation of metal–oxide–semiconductor field effect transistor

This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low-noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)- and common source (CS)-input-matched LNAs are designed where the variation of input impedance over the whole operating band is significantly reduced by applying the multifinger layout technique and employing shunt passive elements for the input device without degenerating the structure, respectively. As part of the proposed SNIM method, a two-dimensional contour plot-based process variation tolerant bias voltage set up protocol is developed which can optimise forward gain (S21), noise figure (NF) and stability factor simultaneously. The regulation of amplifier port parameters with bias settling contour plots and finger parameters results in the proposed SNIM technique. For the CG-input-matched LNA, the post-layout electromagnetic simulated NF is between 3.08 and 4.1 dB, the average power gain of 25.52 dB with a power consumption of 20.19 mW and the CS-input-matched LNA achieves an NF in between 2.772 and 3.04 dB, the average power gain of 17.98 dB while the dissipated power is 20.73 mW.

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain $$\hbox {S}_{21}$$ of $$20.10 \pm 1.65\,\hbox {dB}$$ across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, $$\hbox {S}_{11}$$ , lies below $$-\,10$$ dB from 4.9–9.1 GHz frequency. Moreover, the output reflection ( $$\hbox {S}_{22}$$ ) and reverse isolation ( $$\hbox {S}_{12}$$ ), is below $$-\,10$$ and $$-\,48$$ dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure ( $$\hbox {NF}_{min}$$ ) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of $$\pm \,0.45\,\hbox {dB}$$ in its $$\hbox {NF}_{min}$$ characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is $$-\,4.22$$ dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of $$\pm \,115\,\hbox {ps}$$ and $$\pm \,1.65\,\hbox {dB}$$ , respectively.

1–30 GHz ultra-wideband low noise amplifier with on-chip temperature-compensation circuit

1–30 GHz ultra-wideband low noise amplifier with on-chip temperature-compensation circuit

3-10 GHz ultra-wideband LNA with continuously variable gain for wireless communication

In this letter, a two-stage low-noise amplifier (LNA) with continuously variable gain for 3–10 GHz Ultra-wideband (UWB) application has been realized in 65 nm CMOS technology. A self-biased shunt resistive feedback with source inductive degeneration topology is used to achieve wideband input matching in the first stage; the inductive-peaking technique is introduced to make the gain smooth; and common source amplifier structure is used to realize variable gain in the second stage. The LNA exhibits a continuously variable gain ranging from −13.2 dB to 16.4 dB, a minimum NF of 3.7 dB and power consumption between 11.1 mW and 16.2 mW under a 1.2 V supply voltage. Moreover, the LNA occupies silicon area of 0.12 mm2. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1697–1699, 2016

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

A SiGe LC-ladder low noise amplifier with base resistance match, gain and noise flatness for UWB applications

This study presents a 3.1–10.6GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S21) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33mW power and achieves S21 of 20.65+0.7dB, NF of 2.79+0.2dB over the band of 3.1–10.6GHz. The simulated input third-order intermodulation point (IIP3) is −17dBm at 10GHz.

High-Performance Wideband Low-Noise Amplifier Using Enhanced $\pi$-Match Input Network

A low noise-figure (NF) and high power gain (S21) 3 ~ 10 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity using 0.18 μm CMOS technology is reported. An enhanced π-match input network is used to achieve wideband input impedance matching as well as high and flat S21. To achieve low and flat NF, the pole frequency and pole quality factor of the second-order NF frequency response are tuned to approximate the maximally flat condition. The LNA consumes 18 mW, achieving S11 better than -10 dB for frequency lower than 12.2 GHz and group-delay (GD) variation smaller than ±14.6 ps for frequencies 3 ~ 10 GHz. Additionally, high and flat S21 of 13.7 ± 1.5 dB is achieved for frequencies 1 ~ 12.5 GHz, which means the corresponding 3-dB bandwidth is 11.5 GHz. Furthermore, the LNA achieves minimum NF of 2.2 dB at 4 GHz and NF of 2.3 ± 0.1 dB for frequencies of 3 ~ 10 GHz, one of the best NF results ever reported for a 3 ~ 10 GHz CMOS LNA.

3.2–9.7 GHz ultra-wideband low-noise amplifier with excellent stop-band rejection

A low-power 3.2–9.7 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent stop-band rejection by 0.18 µm CMOS technology is demonstrated. High stop-band rejection is achieved by using a passive bandpass filter (BP-filter) with three finite transmission zeros (in the input terminal), one of which (ωz1=0.9 GHz) is in the low-frequency stop-band and the other two (ωz3 and ωz5) are in the high-frequency stop-band. In addition, an active notch filter is used in the output terminal to introduce another low-frequency stop-band transmission zero (ωz2) at 2.4 GHz. The LNA consumes 4.68 mW and achieves S11 of −10 to −39.5 dB, S21 of 9.3±1.5 dB, and an average NF of 6 dB over the 3.2–9.7 GHz band. The measured stop-band rejection is better than 21.6 dB for frequencies DC–2.5 and 11.2–20 GHz.

3–10 GHz ultra-wideband low-noise amplifier with new matching technique

A low-power and low-noise amplifier with a new input- matching technique using 0.18 µm CMOS technology for ultra-wideband applications is presented. A proposed broadband input match can be acquired easily by selecting an appropriate width of the transistor, which will effectively avoid the usage of the low-Q on-chip inductors in the input network. Moreover, demonstrated is the feasibility of the inter-stage resonator to accomplish bandwidth enhancement without additional power consumption. The IC prototype achieves good performances such as a power gain of 16.2 dB, a better than 10 dB input return loss, and 2.3 dB minimum noise figure while consuming a DC core power of only 6.8 mW.

2.5 dB NF 3.1–10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1–10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only ±16.7 ps across the whole band) using standard 0.13 µm CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S11) of −17.5 to −33.6 dB, output return loss (S22) of −14.4 to −16.3 dB, flat forward gain (S21) of 7.92±0.23 dB, and reverse isolation (S12) of −25.8 to −41.9 dB over the 3.1–10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.

0.18 [micro sign]m 3.1–10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7±17.4 ps group-delay

A 3.1–10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only ±17.4 ps across the whole band) using standard 0.18 µm CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S11) of −9.7 to −19.9 dB, output return loss (S22) of −8.4 to −22.5 dB, flat forward gain (S21) 11.4±0.4 dB, reverse isolation (S12) of −40 to −48 dB, and noise figure of 4.12–5.16 dB over the 3.1–10.6 GHz band of interest. A good 1 dB compression point (P1 dB) of −7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681×657 µm excluding the test pads.