GF Arithmetic Research Articles

RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography

Due to the recent advances in new communication standards, such as 5G New Radio and beyond 5G, and in quantum computing and communications, new requirements for integrating processors into nodes have appeared. These requirements are meant to provide flexibility in the network to reduce operational costs and support diversity in services and load balancing. They are also designed to integrate both new and classical algorithms into efficient and universal platforms, execute specific operations, and attend to tasks with lower latency. Furthermore, some cryptographic algorithms (classical and post-quantum), which are essential to portable devices, share the same arithmetic with error-correction codes. For example, Advanced Encryption Standard (AES), elliptic curve cryptography, Classic McEliece, Hamming Quasi-Cyclic, and Reed-Solomon codes use GF(2^m) arithmetic. As this arithmetic is the basis of many algorithms, a versatile RISC-V Galois field ISA extension is proposed in this work. The RISC-V instruction set extension is implemented and validated using SweRV-EL2 1.3 on a Nexys A7 FPGA. In addition, a five-times acceleration is achieved for AES, Reed-Solomon codes, and Classic McEliece (post-quantum cryptography) at the expense of increasing the logic utilization by 1.27%.

A Low-Power Parallel Architecture for Finite Galois Field GF(2m) Arithmetic Operations for Elliptic Curve Cryptography

A Low-Power Parallel Architecture for Finite Galois Field GF(2<SUP>m</SUP>) Arithmetic Operations for Elliptic Curve Cryptography

Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials

Finite field GF(2m) arithmetic is becoming increasingly important for a variety of different applications including cryptography, error coding theory and computer algebra. Among finite field arithmetic operations, GF(2m) multiplication is of special interest because it is considered the most important building block. GF(2m) multipliers present reduced space and time complexities when the field is generated by some special irreducible polynomials. Among these, irreducible pentanomials of degree m are specially important because they are abundant and there are several eligible candidates for a given m. In this paper, we consider bit-parallel polynomial basis multipliers over the finite field GF(2m) generated using type 2 irreducible pentanomials, for which explicit formulas and algorithms for the computation of the products are given. In this contribution, two new subclasses of type 2 irreducible pentanomials are also introduced. The theoretical complexity analysis proves that the bit-parallel multipliers here presented have the lowest number of XOR gates known to date for similar polynomial basis multipliers based on this type of irreducible pentanomials, while the number of AND gates and the time complexity match the best known results found in the literature.

Low Latency $GF(2^{m})$ Polynomial Basis Multiplier

Finite field GF(2m) arithmetic is becoming increasingly important for a variety of different applications including cryptography, coding theory and computer algebra. Among finite field arithmetic operations, GF(2m) multiplication is of special interest because it is considered the most important building block. This contribution describes a new low latency parallel-in/parallel-out sequential polynomial basis multiplier over GF(2m). For irreducible GF(2m) generating polynomials f(x)=xm+xkt+xkt-1+⋯+xk1+1 with m ≥ 2kt-1, the proposed multiplier has a theoretical latency of 2kt+1 cycles . This latency is the lowest one found in the literature for GF(2m) multipliers. Furthermore, the condition m ≥ 2kt-1 is specially important because the five binary irreducible polynomials recommended by NIST for elliptic curve cryptography (ECC) implementation verify this condition.

On hardware and software implementation of arithmetic in finite fields of characteristic 7 for calculation of pairings

We study scheme (hardware) and program (software) methods of multiplication of polynomials over fields of characteristic 7 in order to apply them to pairing-based cryptographic protocols on hyperelliptic curves of genus three. We consider hardware and software implementations of arithmetic in GF(7), GF(72), GF(7 n ), GF(77n ), and GF(714n ) and estimate the complexity of corresponding schemes and programs.

Versatile processor for GF(pm) arithmetic for use in cryptographic applications

There has been a lot of research in recent years into the implementation of cryptographic algorithms over GF(2m), GF(pm), p≥2 and GF(p), p large prime. A general architecture for a cryptographic processor capable of handling operations for elliptic curve cryptosystems and pairings over any field, and the software developed to generate it, is introduced. The processor implements a ROM instruction set to simplify control of the system and reduce hardware complexity. Efficient scheduling of the data is used to determine the optimum resource requirement for the processor. The post place and route results for a number of generated elliptic curve processors are given.

Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks

The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks (WSN). The design challenges for an efficient WSN mainly lie in two issues: power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte (S-box) transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, 1) The composite field arithmetic in GF((2 4)) 2 was used to implement the compact datapath circuit; 2) A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit (ASIC) on 0.25 μm complementary mental oxide semiconductor (CMOS) process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high-performance cryptographic intellectual property (IP) core for the wireless sensor node chips.

Algorithms and architectures for a flexible elliptic curve cryptography processor

In this paper algorithms and architectures for an new versatile type of elliptic curve cryptography processor over Galois fields GF(2 m ) are presented. Due to its flexibility, it readily permits changes in the system security parameters. The processor has, at its core, a novel method of performing arithmetic in GF(2 m ). The implementation aspects and design trade-offs of such a processor in comparison with more traditional implementations are examined through prototyping on FPGA technology.

An FPGA implementation of a GF(p) ALU for encryption processors

Secure electronic and internet transactions require public key cryptosystems to establish and distribute shared secret information for use in the bulk encryption of data. For security reasons, key sizes are in the region of hundred's of bits. This makes cryptographic procedures slow in software. Hardware accelerators can perform the computationally intensive operations far quicker. Field-Programmable Gate Arrays are well-suited for this application due to their reconfigurability and versatility. Elliptic Curve Cryptosystems over GF(p) have received very little attention to date due to the seemingly more attractive finite field GF(2m). However, we present a GF(p) Arithmetic Logic Unit which can perform 160-bit arithmetic at clock speeds of up to 50 MHz.

An FPGA implementation of a GF( p) ALU for encryption processors

Secure electronic and internet transactions require public key cryptosystems to establish and distribute shared secret information for use in the bulk encryption of data. For security reasons, key sizes are in the region of hundred's of bits. This makes cryptographic procedures slow in software. Hardware accelerators can perform the computationally intensive operations far quicker. Field-Programmable Gate Arrays are well-suited for this application due to their reconfigurability and versatility. Elliptic Curve Cryptosystems over GF( p) have received very little attention to date due to the seemingly more attractive finite field GF(2 m ). However, we present a GF( p) Arithmetic Logic Unit which can perform 160-bit arithmetic at clock speeds of up to 50 MHz.

A compact algorithm for Gaussian elimination over GF(2) implemented on highly parallel computers

Gaussian elimination over GF(2) is used in a number of applications including the factorisation of large integers. The boolean nature of arithmetic in GF(2) makes the task well suited to highly parallel bit-organised computers. A program to work with up to 4096 × 4096 matrices has been developed for the ICL-DAP. A method has been developed that needs no extra storage to store the history of the elimination. The algorithm is presented and its correctness proved.