Gettering Sites Research Articles

Fe Gettering for High-Efficiency Solar Cell Fabrication

The gettering behavior of Fe into Si at 600°C for samples with and without a p+ layer was investigated by deep-level transient spectroscopy. These samples contaminated with Fe at 930°C for 4 h at a concentration of 4.6×1013 cm-3 were annealed at 600°C to induce gettering. The concentration of Fe atoms in the bulk Si markedly decreased with annealing time at 600°C. It was found that the gettering site of Fe is not the p+ layer but the very thin surface layer.

Gettering in silicon-on-insulator wafers: experimental studies and modelling

Buried oxide, which separates the device area from the substrate in silicon-on-insulator (SOI) wafers, forms a diffusion barrier for transition metals in silicon. The impact of this barrier on the efficiency of traditional gettering techniques for iron and copper is evaluated using computer modelling. Several parameters essential for the modelling, such as the diffusivity of iron in SiO2 and the segregation coefficient of iron and copper in SiO2, are verified experimentally. It is found that all available data for the diffusivity of iron in SiO2 (including data points from the literature and our own value of 1.4 × 10−13 cm s−2 at 1100 °C) could be fitted by the equation D(Fe in SiO2) = 2.2 × 10−2 × exp(−3.05 eV/kBT)(cm2 s−1). The solubility of iron in silicon dioxide was found to be 4.5 times to 5.5 times less than that in silicon at temperatures from 1020 °C to 1100 °C, which indicates that iron does not segregate in SiO2. The solubility of Cu in silicon dioxide was determined to be half of that in silicon at 1150 °C and 3.3 times higher than in silicon at 690 °C. Modelling of gettering using these parameters revealed that buried oxide prevents iron from diffusing to gettering sites in the substrate at typical processing temperatures, thus rendering the substrate gettering techniques inefficient. On the other hand, the diffusion barrier protects the device area from contamination from the backside of the wafer. Copper has sufficiently high diffusivity in SiO2 to diffuse through the buried oxide within a short time at 1000 °C; however, it may be difficult to remove copper from the device area because heavily doped areas of the devices could provide competitive gettering sites for copper. Possible gettering strategies for the SOI wafers are discussed.

Hydrogen and helium interactions in Si: phenomena obscure and not-so-obscure

The deliberate use of H- and He-related phenomena in crystalline Si (c-Si) has at times been hampered by concerns of the mobility of these light elements and hence potential device instability. However H is inevitably present in many Si processing steps, though not necessarily in the finished device. Accordingly one could differentiate between a transient or catalytic interaction of H with c-Si, and one where H resides permanently during device operation. We have uncovered phenomena on both domains, and these involve trapping and de-trapping of H by defective regions, thermal activation of latent defects in hydrogenated c-Si, and low-temperature activation of ion implanted dopant atoms. He differs from H principally by its electrical inactivity, but plays a significant role in altering the microstructure. The strong interaction of He with vacancy clusters results in nanocavities that act as excellent gettering sites and also enable localized minority carrier lifetime control. H and He thus offer possibilities for defect and impurity engineering in Si.

Characterization of novel active area silicon avalanche photodiodes operating in the geiger mode

We present a method for characterizing avalanche photodiode (APD) photon-counting detector efficiency as a function of active area. Various shallow-junction silicon APDs having a novel active area were manufactured and tested. We show that cylindrical and checkquerboard-shaped active areas have dark counts two orders of magnitude lower than standard circular devices with an equivalent active area. A parallel implementation of small active areas creates gettering sites for defects to migrate to, which is believed to create relatively defect-free active areas as the perimeter-to-area ratio is increased. However, a compromise between a large perimeter-to-area ratio and a structure useful for practical applications must be considered to optimize the detector.

The thermal stability of iron precipitates in silicon after internal gettering

The re-dissolution behavior of iron gettered at oxide precipitates serving as internal gettering sites was studied in the temperature range from 750°C to 900°C using p-type Czochralski-grown silicon with a boron doping level of 2.5×1014cm−3 and oxide precipitates density of 5×109cm−3. The concentration of interstitial iron and iron-boron pairs was measured by deep-level transient spectroscopy. It was found that the re-dissolved iron concentration can be fitted by an exponential dependence, and the dissolution rate τ−1 had an Arrhenius-type dependence on temperature. The activation energy of the dissolution time constant was found to be 1.47eV. Considering the activation energy of 0.67eV for iron diffusion in silicon, our result implies an effective binding energy of 0.80eV between gettered iron impurities and oxide precipitates. The re-dissolved iron concentration during different heat treatments was simulated with our gettering simulator taking into account this effective binding energy.

Sensitive Copper Detection in P-type CZ Silicon using μPCD

Conventional microwave photoconductive decay (μPCD) method in conjunction with high intensity bias light has been used to study out-diffusion and precipitation of copper in p-type Czochralski (CZ) silicon. The high intensity light is used to activate the precipitation of interstitial copper, which follows Ham’s kinetics and results in a distinctive decrease in the excess carrier lifetime. Results indicate that Cu concentration well below can be detected by this method. It is demonstrated that positive corona charge can be used to prevent out-diffusion of interstitial copper, while negative charge enables copper to freely diffuse to the wafer surfaces. It was observed that the precipitation rate of copper increased significantly when the bias-light intensity is raised above a certain critical level. In addition, the copper precipitation rate was discovered to be much higher in samples which have internal gettering sites. These findings suggest that high intensity light reduces the electrostatic repulsion between positively charged interstitial copper ions and copper precipitates enabling copper to precipitate in the wafer bulk even at a low concentration level, and during high intensity illumination, oxygen precipitates provide effective heterogeneous nucleation sites for copper. © 2003 The Electrochemical Society. All rights reserved.

Study of Cu and Co gettering mechanism using radioactive isotope tracers

The gettering mechanism of Cu and Co in various wafers has been quantitatively studied by the measurement of Cu and Co distribution using radioactive isotope tracer method. We found quantitative gettering of Cu and Co in P/P + epitaxial wafer with polyback seal (PBS) and bulk micro defect (BMD), respectively. On the other hand, P + substrate was not an effective gettering site for Co because of no Coulomb interaction between Co 0 and high boron in the substrate of epitaxial wafer. In the case of Cu, the high boron concentration in the substrate of P/P + epitaxial wafer without PBS has a strong gettering effect due to Coulomb interaction.

Modeling of Competitive Gettering of Iron in Silicon Integrated Circuit Technology

Areas of heavy doping, implantation damage, and lattice strains, which are part of any silicon-integrated circuit device, can provide efficient traps for metals and compete for impurities with intentionally introduced gettering sites. In this article we introduce the concept of competitive gettering between gettering sites and devices and perform modeling of competitive gettering in epi wafers, wafers with internal gettering sites, and silicon-on-insulator (SOI) wafers. The impact of the substrate resistivity, density of oxide precipitates, and denuded zone/epi layer width is analyzed for a wide span of cooling ranges. It is found that the major consequence of the effect of gettering by devices is that by the end of cooling, the metal concentration in the device area can substantially exceed its average concentration in the wafer, and device yield could degrade. This can be prevented by optimizing the substrate gettering properties. Although fast cooling rates inherent in rapid thermal processing represent a challenge for gettering, it is shown that optimized gettering can perform well even if the wafer is cooled in a rapid thermal processing system at a rate between 5 and 100 degrees per second. Our modeling results indicate that SOI wafers behave differently than epitaxial or bulk wafers because the buried oxide layer provides a barrier for diffusion of metals between the device area and the substrate. The last section of the article presents an experimental proof of principle of competitive gettering. © 2003 The Electrochemical Society. All rights reserved.

Comparison of Iron Gettering Effectiveness in Silicon between Ion-Implantation-Induced Damage and Poly-Crystalline Silicon

Iron gettering effectiveness in silicon was compared between poly-crystalline Si and ion-implantation-induced damage. B-doped Czochralski-grown Si wafers with/without poly-crystalline silicon on the backsurface were contaminated with 6×1012 Fe/cm3 and implanted with Si at 50 keV to a dose of 2×1013/cm2. The samples were annealed at a temperature ranging from 700 to 900°C to induce Fe gettering. Poly-crystalline Si was found to be a more effective gettering site than ion-implantation-induced damage and to prevent Fe from being gettered at ion-implantation-induced damage. We consider that the difference of gettering efficiency between ion-implantation-induced damage and poly-crystalline silicon is caused by the difference of the gettering mechanism. When there was no polycrystalline Si and Fe concentration exceeded the solid solubility limit at a given temperature, Fe atoms were gettered at ion-implantation-induced damage. Photoluminescence and deep-level transient spectroscopy measurements revealed that the ion-implantation-induced damage, which gettered Fe, produced a new deep level. We consider that the defects related to this deep revel contain Fe clusters.

EXAFS measurements of metal-decorated nanocavities in Si

This contribution presents a sample preparation methodology to enable the identification, with synchrotron radiation-based analytical techniques, of the gettering sites of metallic impurities on the internal walls of implantation-induced nanocavities in Si substrates. Preliminary results for the Cu–Si and Cu–Cu bond lengths on the internal surface of the nanocavities are reported.

Incorporation of helium-implant-induced cavities near the active regions of metal–oxide–semiconductor devices: Effects on dc electrical characteristics

Cavities, formed by helium implantation and subsequent annealing, have proved to be effective at trapping metal impurities within silicon. This has led to interest in their use as proximity gettering sites. In this investigation, cavity populations were formed by helium implants of energy 40 keV and dose 5×1016 cm−2 followed by annealing at 900 °C. This regime produces cavities with a mean void radius of 20 nm, located between 100 and 350 nm below the silicon surface. The effect of the presence of such cavities near the active areas of 1.2 μm p-type metal–oxide–semiconductor field-effect transistor devices is described. Electrical characterization of wafers, which have been implanted with helium on the front or rear silicon surface, has been carried out to determine whether the inclusion of void populations near the active regions of silicon devices is detrimental. These measurements found no evidence of any detrimental effect on the performance of working devices.

Application of Gate Oxide Integrity to the Evaluation of the Efficiency of Internal and External Gettering Sites in Si Wafers

Application of Gate Oxide Integrity to the Evaluation of the Efficiency of Internal and External Gettering Sites in Si Wafers

Precipitation Kinetics and Recombination Activity of Cu in Si in the Presence of Internal Gettering Sites

Precipitation Kinetics and Recombination Activity of Cu in Si in the Presence of Internal Gettering Sites

Recombination activity of copper in silicon

The carrier recombination activity of copper in n-type and p-type silicon has been investigated. The minority carrier diffusion length has been found to decrease monotonically with increasing copper concentration in n Si and to exhibit a step-like behavior in p-type silicon at Cu concentrations above a certain critical level. It is suggested that the impact of copper on the minority carrier diffusion length is determined by the formation of copper precipitates. This process is retarded in perfect silicon due to the large lattice mismatch between Cu3Si and the silicon lattice and even more retarded in p Si, due to electrostatic repulsion effects between the positively charged copper precipitates and interstitial copper ions. Comparison of the impact of Cu on minority carrier diffusion length obtained with p-Si samples of different resistivity confirmed the electrostatic model. Studies of the impact of copper on minority carrier diffusion length in samples with internal gettering sites indicated that they provide heterogeneous nucleation sites for Cu precipitation at subcritical Cu concentration. Above a certain threshold of Cu concentration, the bulk recombination activity is dominated by quasihomogeneous formation of Cu precipitates, a process that is not detectably affected by the presence of oxide precipitates.

Prevention of impurity gettering in the RP/2 region of ion-implanted silicon by defect engineering

Si + ion implantation into Si under inclined incidence angle was applied to demonstrate that Cu gettering in the region around half of the projected ion range, R P/2, of ion-implanted Si is controlled by the same mechanism working for excess vacancy generation. The obtained results directly relate the appearance of the R P/2 gettering effect to the radiation-induced excess vacancies. Excess vacancies were found to be the source of the dominating gettering sites of Cu at R P/2. Moreover, it is shown that the undesired impurity trapping at R P/2 can be prevented by means of additional Si + implantation into the vacancy-rich region of ion-implanted Si to balance the excess of vacancies. The parameters in order to remove Cu gettering at R P/2 are determined for the additional Si + implantation. If the threshold fluence necessary to remove the Cu gettering at R P/2 is exceeded, the excess vacancies are overcompensated and new interstitial-type dislocation loops form.

Gettering of metal impurities to cavities formed by hydrogen and helium implantation in silicon

Implantation conditions necessary to form a sub-surface depth layer containing cavities by H+ and He+ implantation into Si were determined and discussed. Ion energy and fluence in the two cases were chosen to meet the criteria necessary to form a gettering layer located deeper than the active regions in submicro devices. The results obtained allowed us to determine that under specified conditions for H+ and He+ implantation into Si, a rather thick (Δz∼0.3–0.4μm) layer can be formed which contains the impurity gettering sites. The gettering behaviour for several transition metals, such as Au, Cu, Co and Fe was discussed.

Integrity of ultrathin gate oxides with different oxide thickness, substrate wafers and metallic contaminations

The integrity of ultrathin gate oxides was investigated as a function of polished and epitaxial wafer surfaces with various gettering sites. After intentional contamination of wafers with 1×1011 atoms/cm2 and 5×1012 atoms/cm2 Cu and Ni by a spin-on technique of high reproducibility, we performed 0.18-μm low-thermal-budget CMOS process runs. Thermal oxides were grown with various gate oxides in the range of 5–17 nm. After a MOS-capacitor fabrication we applied a ramped current-density test to study the gate-oxide integrity. Generally, thinner gate oxides exhibited a much more robust behavior than thicker oxides. The gate-oxide integrity was strongly influenced by different gettering sites. Although a higher Ni contamination led to a higher number of gate-oxide failures, Cu contamination exhibited a higher impact on the gate-oxide integrity than Ni.

Gettering of Co in Si by high-energy B ion-implantation and by p/p+ epitaxial Si

Detection and gettering of Co contamination in processed Si is an important issue in integrated circuit fabrication. In this work, Co was intentionally introduced into Si by ion implantation, and its diffusion monitored by secondary ion mass spectroscopy. The surface layer recombination lifetime in p/p+ epitaxial Si is unaffected by the Co at doses of 1×1011 cm−2 or 1×1012 cm−2. In the case of 2.5 MeV, 4×1014 B/cm2 ion implanted bulk Si, two mechanisms for Co redistribution during high temperature furnace, 900 °C, 30 min, processing are evident. First, regions of high boron concentration provide gettering sites for Co contamination. Second, the final distribution of Co in Si reflects ion-implantation induced defect evolution during annealing. Both mechanisms will operate during device processing and will control the effect of the metal on the electrical properties of the Si.

Heavy-Metal (Fe/Ni/Cu) Behavior in Ultrathin Bonded Silicon-On-Insulator (SOI) Wafers Evaluated Using Radioactive Isotope Tracers

The behavior of Fe, Ni and Cu in bonded silicon-on-insulator (SOI) wafers thinned down to 0.5 µm by plasma-assisted chemical etching (PACE) was investigated for the first time by the radioactive isotope tracer method, which can avoid the evaluation errors due to contamination during sample preparation or analysis. When ultrathin bonded SOI wafers without an intentional gettering site were contaminated with Fe or Ni from the surface, Fe and Ni did not diffuse into the substrate through the buried oxide (BOX) layer after annealing in N2(2%O2) ambient at 900°C and 700°C, respectively. Cu easily diffused into the substrate through the BOX layer after annealing at 700°C for 60 min, and was captured at the bonding interface. It was found that the behavior of Ni, which exhibits the same diffusivity in Si as does Cu, was quite different in ultrathin bonded SOI wafers from that in bulk Si wafers due to the BOX layer of the SOI structure.

Gettering efficiencies of polysilicon-, stacking fault- and He-implanted backsides for Cu and Ni

We have studied the gettering efficiencies of copper and nickel in silicon wafers with polysilicon-, stacking fault- and He-implanted backsides. The gettering test begins with a controlled spin-on spiking in the range of low 10 12 atoms cm −2, followed by a metal drive-in at 800°C 30 min −1 under argon atmosphere. The depth profile of the metals was analyzed using inductively coupled plasma-mass spectrometry in combination with a novel chemical, layer-by-layer etching procedure. We were able to reveal the depth profile with a depth resolution of 0.5 μm in each etching step. The gettering efficiency was similar for all backside preparations and always larger for copper than for nickel. We concluded that the backside gettering sites reduced the activation energy of the formation of metal silicides at a given temperature when the solubility limit has been reached. The dependence of the gettering efficiency for the different metal species can be explained by comparing the diffusion coefficients at the temperature of saturation. The higher the diffusion rate at the temperature of saturation, the more efficient the backside gettering. In a second experiment, we examined polysilicon backside gettering of different cooling rates. The gettering efficiency was strongly dependent upon the cooling rate and related to the diffusion rate of the metals. When the cooling rate is high enough, the metals migrate too slowly to reach the wafer backside and precipitate as silicides or metal colonies on defect sites. In these cases, gettering occurred during controlled cooling of the wafers after the metal drive-in.