GeSn pMOSFETs Research Articles

Germanium-Tin Junctionless p-Finfets: Effects of Channel Doping Concentration and Fin Width

High-mobility channel materials are important to extend the CMOS technology to beyond 3-nm node. GeSn p-MOSFETs with a record-high hole mobility of 845 cm2/V-s and a high drive current of > 1850 A/m were demonstrated [1, 2]. While the high-performance GeSn p-FETs were demonstrated, the required complicated fabrication steps remain challenging. A junctionless (JL) FinFET device was proposed to suppress the short-channel effects with easier fabrication steps [3]. Furthermore, for the JL devices, there are no additional ion implantation or annealing steps for the S/D formation, which can prevent Sn segregation or strain relaxation. While the device performance of JL FinFETs can be enhanced by increasing the channel doping concentration, the electrostatic control over the bulk channel in a JL FinFET becomes worse. In this work, we address the effects of the fin width and doping concentration on the device performance of GeSn JL FinFETs. GeSn JL p-FinFETs with fin widths of 10–50 nm are fabricated (Fig. 1 (a)). High-quality p-GeSn films were epitaxially grown on silicon-on-insulator substrates by in-situ doping chemical vapor deposition (CVD) and . HR-XRD results showed that the Ge0.92Sn0.08 layer was fully strained to the underlying relaxed Ge layer with clear Pendellösung fringes around the GeSn peak. Excellent crystallinity and defect-free GeSn/Ge interface can be observed in TEM images. The carrier density and mobility were characterized by Hall measurements. Boron dopants were fully activated up to the level of 1.3 × 1019 cm-3. The device fabrication steps were carried out at temperatures below 400 ◦C to prevent the Sn segregation. After a post-metal annealing step, the drive current was boosted by a factor of 1.5 due to the reduction of the contact resistance by the NiGeSn formation (Fig. 1 (b)). Furthermore, the SS was also improved after the PMA step. To improve the device performance of JL FinFETs, the doping concentration in the GeSn channel was increased by in-situ CVD. The drive current increases with the doping concentration due to the larger channel conductivity (Fig. 1 (c)). Benefiting from the low-temperature processes, JL structure, and the narrow fin width, the best SS is 88 mV/dec and extremely high Ion/Ioff ratios of 105 and 107 were achieved for the overdrive voltages of 0.7 V and 2 V, respectively (Fig. 1 (d)). Last, TCAD simulations were performed to investigate the effects of the channel doping concentration, the fin width, and the defect density at the oxide interface on SS. While for a high performance GeSn JL FinFET, the doping level was increased, the channel cannot be shut off effectively, leading to a higher subthreshold leakage and a poorer SS. To effectively deplete the carriers in the channel, a much reduced fin will be required. While shrinking the devices could improve the SS, the simulation results suggest that reducing the defect density at the high-k/GeSn interface is also crucial for further performance improvements of the GeSn JL FinFETs. [1] M. Liu et al., VLSI Symp. Tech. Dig., Jun. 2014. [2] Y.-S. Huang et al., IEDM Tech. Dig., Dec. 2017. [3] J. Colinge et al., Solid-State Electron., vol. 65, pp. 33–37, Nov. 2011. Figure 1

High-Mobility CVD-Grown Ge/Strained Ge0.9Sn0.1/Ge Quantum-Well pMOSFETs on Si by Optimizing Ge Cap Thickness

The high peak mobility of 509 cm2/ $\text {V}\cdot \text {s}$ of the chemical vapor deposition -grown GeSn pMOSFETs is obtained using 1-nm Ge cap. The Ge cap on GeSn can reduce the scattering of oxide/interface charges and surface roughness for the holes in the GeSn quantum wells. However, the thick cap induces holes in the Ge cap itself, leading lower mobility than GeSn channels. The on current is enhanced by external stress due to the effective mass reduction. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.

Strained Germanium–Tin (GeSn) P-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Featuring High Effective Hole Mobility

Compressively strained \(\hbox {Ge}_{0.973}\hbox {Sn}_{0.027}\) and \(\hbox {Ge}_{0.925}\hbox {Sn}_{0.075}\) p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated with low-temperature \(\hbox {Si}_{2}\hbox {H}_{6}\) surface passivation. High crystallinity GeSn films epitaxially grown on a Ge(001) substrate are used for the device fabrication. The impacts of the Sn composition on the subthreshold swing \(S\), threshold voltage \(V_\mathrm{TH}\), on-state current \(I_\mathrm{ON}\), and effective hole mobility \(\mu _\mathrm{eff}\) of the devices are investigated. GeSn pMOSFETs with different Sn compositions show a similar \(S\), indicating almost the same midgap density of interface states \(D_\mathrm{it}\). A positive shift of \(V_\mathrm{TH}\) with an increase of the Sn composition is observed. A \(\hbox {Ge}_{0.925}\hbox {Sn}_{0.075}\) pMOSFET exhibits a significant improvement in \(I_\mathrm{ON}\) as compared to a device with a lower Sn composition, which is due to the superior hole mobility in a device with a higher Sn composition. \(\hbox {Ge}_{0.925}\hbox {Sn}_{0.075}\) pMOSFETs achieve a peak effective hole mobility \(\mu _\mathrm{eff}\) of \(500\,\hbox {cm}^{2}{\cdot }\hbox {V}^{-1}{\cdot } \hbox {s}^{-1}\), which is much higher than that of \(\hbox {Ge}_{0.973}\hbox {Sn}_{0.027}\) devices. The enhancement of the compressive strain and chemical effect in the channel region with increased Sn composition leads to an improvement of \(\mu _\mathrm{eff}\).

Strained GeSn p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors With In Situ Si2H6 Surface Passivation: Impact of Sn Composition

We report a study about the impact of Sn composition on the performance of strained germanium-tin (GeSn) pMOSFETs. GeSn pMOSFETs with Sn compositions of 0.027, 0.040, and 0.075 were fabricated on Ge(001) with an in situ Si 2 H 6 passivation. Enhancement in drive current and transconductance is obtained for GeSn pMOSFETs with higher Sn composition due to the smaller capacitance equivalent thickness, the reduced source/drain resistance, and the improved effective hole mobility μeff. Right shift of threshold voltage with Sn composition is observed for the devices. Ge 0.973 Sn 0.027 , Ge 0.960 Sn 0.040 , and Ge 0.925 Sn 0.075 pMOSFETs demonstrate the peak μ eff of 340, 378, and 496 cm 2 /Vs, respectively. At an inversion charge density of 5 × 10 12 cm -2 , Ge 0.925 Sn 0.075 pMOSFETs demonstrate 36% and 24% enhancement in μ eff compared with Ge 0.973 Sn 0.027 and Ge 0.960 Sn 0.040 devices, respectively. Simulation shows that the enhancement in μeff with Sn composition is resulted from the reduction of hole effective mass and intervalley scattering between heavy and light holes caused by the increased compressive strain.

Invited; Solid Phase Epitaxy of GeSn Alloys on Silicon and Integration in MOSFET Devices

Single crystalline Ge compounds (SiGe, GeSn) have interesting electrical and optical properties [1], rendering them well-suited to a wide variety of applications. GeSn has been predicted to exhibit carrier mobilities exceeding that of Ge [2], which makes this material suitable as a channel material for high-speed complementary metal-oxide semiconductor (CMOS) technology [3]. In addition to increased carrier mobility, the GeSn material system is interesting for its optical properties. GeSn exhibits a direct band gap between 0.61 and 0.35 eV for Sn concentrations between 6 and 15 % [4]. This makes it much better fit for optoelectronic applications than Si and Ge, especially at long wavelengths.Epitaxial growth of GeSn on Si substrates poses several challenges including a limited solubility of Sn in Ge (0.5%), compositional fluctuations, Sn segregation and a large lattice mismatch (>4%). It is critical to suppress these effects while simultaneously optimizing the GeSn layer characteristics for the basis of high performance devices.Recently, we demonstrated the growth of single crystalline GeSn layers with excellent structural quality grown on Si(111) substrates, by solid phase epitaxy (SPE) of amorphous GeSn alloys[5]. This technique has an advantage in the realization of thin GeSn layers directly on Si. We do not use surfactants, a capping layer, nor a buffer layer. Amorphous GeSn layers are obtained by the co-evaporation of Ge and Sn atoms, with beam equivalent pressures of 1.33 x 10-7 Torr for Ge and 9 x 10-9 Torr for Sn, while exposing the substrate to a N2 flux with a beam equivalent pressure of about 1 x 10-5 Torr, at a deposition temperature around RT. Subsequent annealing transforms the amorphous GeSn into a single crystalline layer via solid phase epitaxy. Excellent structural quality is demonstrated for layers with up to 6.1 % of Sn. The GeSn layers show tensile strain (up to +0.34%), which lowers the difference between the direct and indirect band transition and makes this method promising for obtaining direct band gap group IV layers. GeSn with 4.5% Sn shows increased optical absorption compared to Ge and an optical band gap of 0.52 eV. Furthermore, the surface and interface are smooth (RMS roughness < 1 nm), despite the relaxation of the layers.Additional structural investigation by XRD and TEM showed the presence of twin defects in the GeSn layers after crystallization. These defects can have a significant impact on the carrier mobility and it is therefore important to suppress the formation of twin defects during crystallization. The formation of twin defects is likely related to the presence of contaminants, in particular oxygen, at the interface between the crystalline substrate and the amorphous layer leading to the roughening of the amorphous-crystalline interface during SPE growth. We have developed a 2-step deposition process which successfully suppresses the formation of such twin defects.Additionally, we demonstrate excellent electrical properties of the GeSn layers by the fabrication of depletion-mode GeSn pMOSFETs on Si(111) using SPE of amorphous GeSn layers, TaN/Al2O3 metal-gate/high-k gate stacks, and Ni-based metal S/D contacts. The GeSn MOSFET devices show +100% improvement in hole mobility with respect to bulk Si and good transfer characteristics with On/Off ratio of ~100 for ultrathin (<10 nm) GeSn layers on Si [6].Finally, we also demonstrate successful crystallization of amorphous SiGe layers, deposited by plasma enhanced chemical vapor deposition (PECVD) on Si substrates and annealing in N2 atmosphere. The SiGe layers show excellent structural quality for compositions ranging from Ge- to Si-rich.[1] J. Kouvetakis et al., Ann. Rev. Mater. Res. 36, 497 (2006)[2] J. D. Sau and M. L. Cohen, Phys. Rev. B 75, 045208 (2007)[3] C. Merckling et al., Appl. Phys. Lett. 11, 192110 (2011)[4] G. He and H. A. Atwater, Phys. Rev. Lett. 79, 1937 (1997)[5] R. R. Lieten et al., Appl. Phys. Lett. 102, 052106 (2013)[6] R. R. Lieten et al., Appl. Phys. Express 6, 101301 (2013)

Hole Mobility Enhancement in Compressively Strained ${\rm Ge}_{0.93}{\rm Sn}_{0.07}$ pMOSFETs

Germanium tin (GeSn) pMOSFETs with channel Sn composition of 7% are fabricated using a low thermal budget process. GeSn pMOSFETs show enhancement in hole mobility over control Ge devices by 85% in high inversion charge density regime. Hole mobility improvement observed in GeSn channel pMOSFETs compared with Ge control is due to the biaxial compressive strain in GeSn resulting from epitaxial growth of GeSn thin films on relaxed Ge buffer layers.

High Hole Mobility in Strained Germanium-Tin (GeSn) Channel pMOSFET Fabricated on (111) Substrate

We report the demonstration of strained GeSn channel pMOSFETs on (111)- and (100)-oriented Ge substrates. The Sn composition is 4.1%. The device interface is passivated using (NH4)2S solution. Compared to devices on Ge(100), GeSn pMOSFETs on Ge(111) demonstrate a 20% enhancement in effective hole mobility at an inversion charge density (Qinv) of 2 × 1013 cm-2.