Germanium-on-insulator Substrates Research Articles

Schottky Barrier Height Extraction in Ohmic Regime: Contacts on Fully Processed GeOI Substrates

The problematics of contacts optimization on germanium metal-oxide-semiconductor field-effect transistors suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals on Ge were so far mostly investigated on weakly n-doped samples under the pure thermionic emission regime. These experimental conditions are suitable for an accurate extraction; the measured Schottky barrier height (SBH) being usually large and linked to the interfacial current density by a relatively simple Arrhenius relationship. However, a device-oriented approach would consist in meeting the contact resistivity requirements in the ohmic regime for metallic contacts on a highly doped semiconductor (e.g., doped source and drain) through the choice of metal, interface preparation, and doping conditions. We hereby detail SBH extractions based on contact resistance measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully processed germanium-on-insulator (GeOI) samples with Ti-based contacts, yielding effective barriers of for electrons and for holes. The method provides a good physical understanding of the technological factors impacting the electrical properties, enabling to define paths toward ohmic-contact optimization in the context of device integration on GeOI.

Formation of Si- and Ge-based Full-Heusler Alloy Thin Films using SOI and GOI Substrates for the Half-metallic Source and Drain of Spin Transistors

The paper presents a novel preparation technique for Si- and Ge-based half-metallic full-Heusler alloy thin films, utilizing silicon-on-insulator (SOI) and germanium-on-insulator (GOI) substrates, respectively. Full-Heusler Co2FeSi (Co2FeGe) alloy thin films were successfully formed by thermally activated silicidation (germanidation) reaction between an ultra-thin SOI (GOI) layer and Co/Fe layers deposited on it. This technique can easily produce fully ordered L21 structure that is necessary for the half-metallicity of full-Heusler alloys. The proposed technique is compatible with metal source/drain formation process in advanced CMOS technology and would be applicable to the fabrication of the half-metallic source/drain of MOSFET type of spin transistors.

Germanium oxynitride (GeOxNy) as a back interface passivation layer for Germanium-on-insulator substrates

This paper describes the development of a GeOxNy surface passivation of germanium, which is mandatory for microelectronics germanium-on-insulator (GeOI) substrate fabrication. Indeed, germanium surface reactivity in ambient atmosphere requires the development of Ge surface passivation in order to provide an electrically acceptable interface between the active layer and the buried oxide (BOX) of GeOI substrates. In this paper, GeOI substrates with a passivation interlayer between the Ge film and the BOX were fabricated using the Smart Cut™ technology. Plasma treatments produced a germanium oxynitride (GeOxNy) passivation interlayer with a nitrogen concentration up to 40% and thickness of 3nm. Electrical activity in such GeOI active layer was investigated with pseudo-metal-oxide-semiconductor field effect transistor measurements. Electron mobility reaches a value of 670cm2V−1s−1, notably higher than those typically reported on nonpassivated GeOI structures.

Forming Gas Annealing Characteristics of Germanium-on-Insulator Substrates

Large-area layer transfer of germanium-on-insulator (GeOI) substrates has been fabricated by ion-cut processes. Pseudo-MOSFET structure was employed to characterize interface trap density, interface fixed charge density, interface carrier mobility, and bulk carrier mobility of these GeOI substrates with various annealing conditions in forming gas ambient. High-temperature annealing in the vicinity of 500degC-600degC has shown the best carrier mobilities, with the interface trap density and the interface fixed charge density as low as 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> q/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The extracted bulk hole mobility of the annealed GeOI is near 500 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /( V middots), which is higher than that of silicon [300 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(V middots)] at the same doping concentration level.

Fabrication of Thick Germanium-on-Insulator (GeOI) Substrates

Fabrication of germanium-on-insulator (GeOI) substrates with a 160-nm-thick Ge layer is reported. Such thick GeOI substrates were fabricated by thermal intermixing and subsequent condensation of epitaxially grown high-Ge- content SiGe on Si-on-insulator (SOI) substrates. Transmission electron microscopy revealed that the GeOI layer was single crystalline. The high-resolution rocking curve and reciprocal lattice map obtained from X-ray diffraction measurements showed a relaxed GeOI. This was further confirmed by micro-Raman measurements, where the Ge-Ge optical phonon peak shift represented a nearly strain-free Ge layer. Using this methodology, GeOI substrates with Ge layers 120–160 nm thick have been fabricated with thickness variations of less than 4 nm across 200 mm wafers.

Study of the Surface Cleaning of GOI and SGOI Substrates for Ge Epitaxial Growth

An effective wet cleaning process, optimized for low temperature Ge epitaxy on thin Ge or SiGe structures with reduced surface roughening, is proposed. It is found that the HF+HCl cleaning is the most effective wet cleaning method that is applicable to the low temperature thermal cleaning. It is also found that temperature of the thermal cleaning appropriate for thin Germanium on Insulator (GOI) substrates is approximately 450ºC. Moreover, the successful formation of the strained-GOI structures is demonstrated by applying these wet and thermal cleaning processes to thin Silicon-Germanium on Insulator (SGOI) substrates.

Nickel Germanide Formation on Condensed Ge Layer for Ge-on-Insulator Device Application

As an effort for realizing a germanium-on-insulator (GOI) device, a method of fabricating a GOI substrate and a technique for forming nickel germanide by a multistep annealing method are presented in this paper. A GOI substrate was fabricated by a germanium condensation technique, that involves a new approach of SiGe epitaxial growth on a silicon-on-insulator (SOI) substrate at a certain modulating gas ratio (Si2H6/GeH4). From the results of atomic force microscopy (AFM), X-ray diffractometer (XRD) and Raman spectroscopy measurements, it was found that this technique can be practically used for GOI substrate fabrication. The novel nickel germanide formation technique with the multistep annealing method was also studied on a condensed GOI layer. A NiGe layer with a low sheet resistance (6.5 Ω/sq.) was obtained at 500 °C. This result confirmed that this method is suitable for nickel germanide formation for fabricating GOI MOSFETs with low source/drain resistances. These technologies are applicable to GOI device fabrication.

Fabrication and characterization of InGaP/GaAs heterojunction bipolar transistors on GOI substrates

In this letter, we report the first demonstration of InGaP/GaAs heterojunction bipolar transistors (HBTs) on germanium-on-insulator (GOI) substrates. We have performed physical characterization of the epitaxial layers to verify the high quality of the III-V epitaxial material grown on the GOI substrates and performed dc characterization of large-area InGaP/GaAs HBTs fabricated on the substrates. The InGaP/GaAs HBTs realized on GOI substrates were compared with identical devices grown on bulk germanium substrates and similar devices on semi-insulating GaAs substrates.

Dopant Activation in bulk germanium and Germanium-on-Insulator

ABSTRACTHigh levels of electrical activation of both p- and n-type dopants are realized by pre-amorphization implantation (PAI) in bulk germanium wafers and germanium-on-insulator (GOI) substrates. In bulk germanium, p-type dopant yields an electrical activated concentration of 1.5×1020 /cm3 after a 400°C rapid thermal annealing (RTA), which is one order higher than obtained for samples without PAI. N-type dopants also show comparable improvement as 1×1020 /cm3 after 600°C RTA. Both results are the highest ever being reported and are sufficient for advanced CMOS applications. PAI was also employed in dopant activation for GOI substrates. Carrier concentrations of 6×1020 /cm3 and 5×1019 /cm3 were observed for p- and n-type dopants respectively after identical RTA conditions as for bulk germanium counterparts. Hydrogen incorporated in GOI wafers which were prepared by Smart-Cut™ approach may be responsible for the discrepancy of activated concentrations between bulk germanium and GOI. Nevertheless, PAI shows the promise of dopant activation in germanium and can be readily adopted in current CMOS processes.