The authors present a new hardware efficient design approach and the associated intellectual property (IP) core design for a one-dimensional (1-D) discrete Fourier transform (DFT). They optimise the proposed DFT design, at both the algorithmic and architectural levels, to provide low hardware cost. At the algorithmic level, first a radix-2c algorithm is used to split a 1-D length-N DFT into multiple 1-D length-N/2c DFTs to facilitate computation sharing between parallel DFT outputs. Then, the length-N/2c DFT is formulated into cyclic convolution form to facilitate the reduction of hardware cost. By applying a word-level sharing technique to explore the symmetries of DFT coefficients, four parallel outputs are obtained simultaneously for each length-N/2c DFT. At the architectural level, the design is implemented with a filter-based architecture that can be optimised by bit-level sub-expression sharing. This facilitates the efficient implementation of multiple complex constant multiplications through shifting and addition operations. Compared with some existing designs, the proposed DFT design has lower hardware cost and better timing performance. Moreover, to facilitate design exploration of system integrators using the system-on-chip (SoC) design, the proposed DFT design is realised in soft core format possessing the flexibility of parameter configurations through a graphic user interface (GUI), signal-to-noise (SNR) calculation on the proposed DFT design with finite wordlength effects, and automatic generation of synthesisable VERILOG codes, synthesis scripts, and testbenches. Using the proposed DFT IP design environment, the system integrators can easily generate the desired DFT/IDFT IP core to meet different SoC applications that encapsulate the DFT/IDFT design. An example of the multimedia applications, artificial reverberation on MPEG audio, of the proposed DFT/IDFT IP core is introduced.
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Jun 1, 2006
E Stip 
Open Access