General-purpose Parallel Architectures Research Articles

Performance analysis and structured parallelisation of the space–time adaptive processing computational kernel on multi-core architectures

The development of radar systems on general-purpose off-the-shelf parallel hardware represents an effective means of providing efficient implementations with reasonable realisation costs. However, the fulfilment of the required real-time constraints poses serious problems of performance and efficiency: parallel architectures need to be exploited at best, providing scalable parallelisations able to reach the desired throughput and latency levels. In this paper we discuss the implementation issues of the computational kernel of a well-known radar filtering technique – the space–time adaptive processing – on today's general-purpose parallel architectures (multi-/many-core platforms). In order to address the performance constraints imposed by the real-time implementation of this filtering technique, we apply a structured approach (structured parallel programing) to develop parallel computations as instances and compositions of well-known parallelisation patterns. This paper provides a thorough description of the implementation issues and discusses the performance peaks achievable on a broad range of existing multi-core architectures.

Integrated performance models for spmd applications and mimd architectures

This paper introduces queuing network models for the performance analysis of SPMD applications executed on general-purpose parallel architectures such as MIMD and clusters of workstations. The models are based on the pattern of computation, communication, and I/O operations of typical parallel applications. Analysis of the models leads to the definition of speedup surfaces which capture the relative influence of processors and I/O parallelism and show the effects of different hardware and software components on the performance. Since the parameters of the models correspond to measurable program and hardware characteristics, the models can be used to anticipate the performance behavior of a parallel application as a function of the target architecture (i.e., number of processors, number of disks, I/O topology, etc).

Integrated performance models for SPMD applications and MIMD architectures

Introduces queuing network models for the performance analysis of SPMD (single-program, multiple-data) applications executed on general-purpose parallel architectures such as MIMD (multiple-input, multiple data) and clusters of workstations. The models are based on the pattern of computation, communication and I/O operations of typical parallel applications. Analysis of the models leads to the definition of speedup surfaces which capture the relative influence of processors and I/O parallelism and show the effects of different hardware and software components on the performance. Since the parameters of the models correspond to measurable program and hardware characteristics, the models can be used to anticipate the performance behavior of a parallel application as a function of the target architecture (i.e. the number of processors, number of disks, I/O topology, etc.).

Minimizing communication in the bitonic sort

This paper presents bitonic sorting schemes for special-purpose parallel architectures such as sorting networks and for general-purpose parallel architectures such as SIMD and/or MIMD computers. First, bitonic sorting algorithms for shared-memory SIMD and/or MIMD computers are developed. Shared-memory accesses through the interconnection network of shared memory SIMD and/or MIMD computers can be very time consuming. A scheme is introduced which reduces the number of such accesses. This scheme is based on the parity strategy which is the main idea of the paper. By reducing the communication through the network, a performance improvement is achieved. Second, a recirculating bitonic sorting network is presented, which is composed of one level of N/2 comparators plus an /spl Omega/-network of (log N-1) switch levels. This network reduces the cost complexity to O(N log N) compared with the O(N log/sup 2/ N) of the original bitonic sorting network, while preserving the same time complexity. Finally, a simplified multistage bitonic sorting network, is presented. For simplifying the interlevel wiring, the parity strategy is used, so N/2 keys are wired straight through the network.

A Flexible Algorithm for Multiprocessor Ray Tracing

Ray tracing programs are widely used to generate photo-realistic images, but the high computation time may discourage their implementation on single-processor machines; moreover, cost reduction of multi-processor general purpose architectures makes parallel rendering an attractive field of research. We propose a new algorithm which addresses the main issues of a parallel implementation of ray tracing on a message-passing-based machine. We adopt efficient strategies for dynamic workload distribution among processors, task synchronization and communication delay reduction. The resulting implementation is highly flexible, since any number of processors can be employed without introducing synchronization problems. We show an implementation of our algorithm on an nCUBE 2 supercomputer which is a general purpose parallel architecture with distributed memory. A theoretical evaluation of our algorithm allows us to identify a decreasing function for rendering times; the considered examples confirm the theoretical expectations showing that the efficiency of our system may reach up to the 91% of the value achievable by dividing the sequential rendering time by the number of processors employed.

An introduction to parallel rendering

In computer graphics, rendering is the process by which an abstract description of a scene is converted to an image. When the scene is complex, or when high-quality images or high frame rates are required, the rendering process becomes computationally demanding. To provide the necessary levels of performance, parallel computing techniques must be brought to bear. Today, parallel hardware is routinely used in graphics workstations, and numerous software-based rendering systems have been developed for general-purpose parallel architectures. This article provides an overview of the parallel rendering field, encompassing both hardware and software systems. The focus is on the underlying concepts and the issues which arise in the design of parallel renderers. We examine the different types of parallelism and how they can be applied in rendering applications. Concepts from parallel computing, such as data decomposition and load balancing, are considered in relation to the rendering problem. Our survey explores a number of practical considerations as well, including the choice of architectural platform, communication and memory requirements, and the problem of image assembly and display. We illustrate the discussion with numerous examples from the parallel rendering literature, representing most of the principal rendering methods currently used in computer graphics.

Scalability, portability and predictability: The BSP approach to parallel programming

General purpose parallel computing systems come in a variety of forms. We have various kinds of distributed memory architectures, shared memory multiprocessors, and clusters of workstations. New technologies may increase this range still further. Can one hope to design portable and scalable parallel software in the face of such architectural diversity? In this paper we show that it is indeed possible to produce fully portable parallel software which will run with highly efficient, scalable and predictable performance on any general purpose parallel architecture. The approach we describe is based on the bulk synchronous parallel (BSP) model of computation. The BSP model provides a simple, unified framework for the design and programming of all kinds of general purpose parallel systems. Over the last few years, a number of important research activities in algorithms and architectures have been pursued as part of this new approach to scalable parallel computing. In this paper we give some simple BSP algorithms and show how they can be expressed as programs. We also briefly describe some of the BSP programming language developments which are now being pursued.

BENCHMARKING LATTICE-BASED APPLICATIONS ON PARALLEL ARCHITECTURES

The numerical analysis and solution of many physics and engineering problems is based on lattice-oriented algorithms. The Cellular Neural Network (CNN) computational paradigm embodies a wide set of grid problems characterized by locality of information exchanges among lattice points. Performance analysis tests using CNN-based algorithms may provide insights into the performance achievable by a given parallel architecture, with respect to a wide class of lattice problems. In this paper a message passing version of a general CNN-based algorithm is implemented and optimized for three general purpose parallel architectures: Connection Machine CM-5, Cray T3D, and IBM SP2. Separate measurements on computations and communications of the algorithm allow us to evaluate processing node and network communication performance of the machines. Moreover. the overall performance of the full application is analyzed, in order to understand the scalability and the range of applicability of this prototype of lattice problem.

A real-time photo-realistic visual flythrough

In this paper we present a comprehensive flythrough system which generates photo-realistic images in true real-time. The high performance is due to an innovative rendering algorithm based on a discrete ray casting approach, accelerated by ray coherence and multiresolution traversal. The terrain as well as the 3D objects are represented by a textured mapped voxel-based model. The system is based on a pure software algorithm and is thus portable. It was first implemented on a workstation and then ported to a general-purpose parallel architecture to achieve real-time performance.

Medical volume visualization on general-purpose parallel architectures.

Parallel volume visualization is of interest to a variety of application areas since current single-processor systems fall short in interactively rendering complex, large-sized datasets. This article presents a survey of volume-visualization methods on general-purpose parallel architectures, with special attention being paid to medical imaging applications. First, the various approaches to volume visualization are briefly discussed, followed by a description of relevant aspects of parallel architectures. Next, the implications of the various architectures are illustrated on the basis of a number of existing implementations of visualization algorithms on parallel architectures and their results. For parallel volume visualization, multiple instruction, multiple data (MIMD) architectures are found to be superior to single instruction, multiple data (SIMD) architectures. The latter type suffers from a lack of performance as well as flexibility. For most applications of interactive volume visualization, including the important area of medical imaging, shared memory MIMD architectures are preferred over distributed memory MIMD architectures. The ease of programming of shared memory architectures allows existing algorithms to be readily implemented without loss of performance or flexibility.

Simulation and visualization tools for link-based parallel architectures

Parallel systems are wellknown solutions to satisfy the demand of computing capabilities, but parallel computer design involves difficult hardware/software tradeoffs. Standard general purpose parallel architectures don't exist, only some particular architectures are used to solve specific problems. In such complex systems the performance measurement is important to evaluate several situations for existing architectures or for systems in designing phase. This performance is highly influenced by factors as interconnection scheme, granularity, computing/communication ratio, algorithm topology and operating system policies. Interaction between these factors is not easy to understand and often unpredictable. Simulation has proved to be useful as a tool for system design and performance evaluation, allowing a simple way to compare different alternatives. In this paper, an integrated simulation environment for the design and evaluation of parallel computing systems is presented. It has been designed for a large-grain data flow programming model, which we call Weighted Behavioral Graph (WBG). This formalism allows the representation of both the static and dynamic properties of the program graph. The simulation environment provides facilities for the program and interconnection graph's specification, as well as the scheduler and router policy's selection. An icon based, multiwindow graphic front end allows for a friendly man-machine interface, thus reducing the model's development cycle.

Petri net performance modeling of a modified mesh-connected parallel computer

A new message-passing computer architecture called the modified mesh-connected parallel computer (MMCPC) is proposed and studied. The MMCPC is designed to be a general-purpose parallel architecture suitable for wafer scale integration. Stochastic Petri nets (SPN) are used to model the behavior of the MMCPC. Both the one-dimensional and two-dimensional SPN models of the MMCPC are presented.

Parallel algorithms and architectures

In this paper we consider some of the central issues involved in the design of parallel algorithms. We describe several efficient algorithms for idealised shared memory architectures and draw some conclusions as to what would be required to implement them on a realistic physical architecture, i.e. one with distributed memory. We also describe some systolic algorithms for matrix computations, sequence comparison and molecular modelling, and briefly discuss their implementation on arrays of transputers. In the final section we discuss the question of whether the current preoccupation with architectural details in parallel algorithm design is likely to persist. We briefly describe some techniques which show that a physically realistic general purpose parallel architecture based on distributed memory can be constructed which will execute any shared memory parallel algorithm with no significant overhead due to communication. We thus have the attractive prospect in the very near future of architectural independence in parallel algorithm design.

On the promise of general-purpose parallel computing

It has become generally accepted that continued improvements in high-performance scientific computation will be achieved only through the ‘exploitation of parallelism’. Despite the nebulous nature of this expression, enthusiasm for the potential of parallel computing has led to calls for improvements in computational performance of more than a thousand-fold in the next few years, or for what is sometimes referred to as a Teraflop (one trillion floating-point operations per second) Computer. Such a system is envisioned as a general-purpose tool for accelerating progress in such widely varied applications as astronomy, biochemistry, circuit analysis, computational fluid dynamics, global economic modeling, high energy physics, materials science, structural analysis, and weather prediction. Although parallel architectures appear to offer the greatest promise for significant improvements in overall computational performance, it is not yet clear whether a general-purpose parallel architecture can realize the large increases solicited by the scientific community. This note will take a practical look at the prospect for general-purpose parallel computation and will consider some of the potential limitations by using a simple parametric model of computational performance.