Ge Virtual Substrates Research Articles

Light Emission of Sn/Ge MQW pin Diodes on Si

Sn/Ge multi-quantum well diodes integrated on Si were grown pseudomorphically on Ge virtual substrates on Si using molecular beam epitaxy. Temperature-dependent electroluminescence analyses were conducted on these devices across a range of temperatures, from 290 K to 12 K. This analysis identified four distinct energy transitions across the entire temperature range. Two of the peaks were observed at high temperatures and were no longer discernible as the temperature decreased. The remaining two peaks were only measured at low temperatures. By analyzing them with a Ge reference diode, one of the peaks was identified as a defect peak. The intensity of the other peak increased as the temperature decreased, which is consistent with the behavior of a direct transition in an indirect semiconductor material.

Group-IV based pin photodetectors for C-band application

GeSn photodetectors with Sn contents between 0% and 6.5% were grown pseudomorphically on Ge virtual substrates on Si by molecular beam epitaxy. Based on the similar functional dependence of the current-voltage characteristics, we conclude that a similar crystal defect is the cause of the recombination/generation centers in both the GeSn and the Ge reference sample. We found that dislocations are not the predominant recombination type. The signal-to-background ratio is a proper quantitative measure for the comparison of heterostructure photodetectors and with near zero bias operation in the C-band, the values of around 104 were obtained with 1 mW light input. For C-band operation, the optimal Sn contents are found to be between 2% and 4%.

Epitaxial growth of Nd2O3 layers on virtual SiGe substrates on Si(111)

This study explores the growth and structural characteristics of Nd2O3 layers on virtual germanium-rich SiGe substrates on Si(111). We focus on the emergence of the hexagonal phase depending on the stoichiometry of the virtual substrate. X-ray diffraction measurements reveal a hexagonal phase when Nd2O3 is grown directly on Si(111), while growth on Ge leads to a cubic oxide structure. On SiGe layers, the growth of the oxide results in a mixed phase containing hexagonal and cubic regions, regardless of the Ge content. The cubic structure grown on virtual Ge substrates exhibits strong tensile strain, while layers grown on SiGe layers show no strain. In situ growth control via electron diffraction shows a dependence of the oxide structure of the surface reconstruction of the virtual substrate. Growth on a 7×7 reconstruction leads to hexagonal parts on Si-based substrates, while growth on c(2×8) results in cubic oxide growth on Ge. Furthermore, oxide layers grown on virtual SiGe substrates form an interfacial silicate layer. The thickness of the interfacial layer is influenced by the Si content and the structure of the oxide layer enabling oxygen diffusion pathways.

Nuclear Spin-Depleted, Isotopically Enriched 70 Ge/28 Si70 Ge Quantum Wells.

The p-symmetry of the hole wavefunction is associated with a weaker hyperfine interaction, which makes hole spin qubits attractive candidates to implement quantum processors. However, recent studies demonstrate that hole qubits are still very sensitive to nuclear spin bath, thus highlighting the need for nuclear spin-free germanium (Ge) qubits to suppress this decoherence channel. Herein, this work demonstrates the epitaxial growth of 73 Ge- and 29 Si-depleted, isotopically enriched 70 Ge/silicon-germanium (SiGe) quantum wells. The growth is achieved by reduced pressure chemical vapor deposition using isotopically purified monogermane 70 GeH4 and monosilane 28 SiH4 with an isotopic purity higher than 99.9% and 99.99%, respectively. The quantum wells consist of a series of 70 Ge/SiGe heterostructures grown on Si wafers. The isotopic purity is investigated using atom probe tomography (APT) following an analytical procedure addressing the discrepancies caused by the overlap of isotope peaks in mass spectra. The nuclear spin background is found to be sensitive to the growth conditions with the lowest concentration of 73 Ge and 29 Si is below 0.01% in the Ge well and SiGe barriers. The measured average distance between nuclear spins reaches 3-4 nm in 70 Ge/28 Si70 Ge, which is an order of magnitude larger than in natural Ge/SiGe heterostructures.The spread of the hole wavefunction and the residual nuclear spin background in APT voluminals comparable to the size of realistic quantum dots are also discussed.

Harvesting strong photoluminescence of physical vapor deposited GeSn with record high deposition temperature

In this work, strong photoluminescence (PL) from physical vapor deposited GeSn on Ge-buffered Si is harvested by pursuing high deposition temperature. High-quality Ge0.938Sn0.062 films are obtained through sputtering epitaxy at a record high temperature of 405 °C. The PL peak intensity of the sputtering-grown GeSn is enhanced by 21 times compared to that of GeSn with similar Sn content grown by molecular beam epitaxy at 150 °C. The PL intensity ratio between the sputtering-grown GeSn and Ge virtual substrate reaches a value of 18. Power-dependent and temperature-dependent PL characterizations demonstrate that band-to-band recombination dominates in the sputtering-grown GeSn film. The results indicate that high-temperature sputtering epitaxy, which has the merit of low cost and high-productivity potential, is promising for preparing high-quality GeSn films for optoelectronic applications.

Ge1-xSnx/Si1-ySny SLs lattice-matched to Ge for 1.55 μm lasers

GeSn is a promising material for fabricating light sources on Si integrated circuits. Because the lattice constant of GeSn is larger than that of Ge, GeSn lasers are grown on relaxed GeSn buffers or Ge virtual substrates, with edge dislocations in the interfaces. A structure of Ge1-xSnx/Si1-ySny SLs lattice-matched to Ge is proposed to overcome this drawback. Band structure was calculated with different Sn contents and thicknesses of GeSn and SiSn. Light emission at 1.55 μm was achieved with 0.9 nm GeSn0.11/ 3.9 nm SiSn0.195 SLs. A graded-index separate-confinement heterostructure laser was designed with the proposed SLs of 8 periods and its performance was investigated. The TE modal gain was dominant over TM modal gain, due to the top valence band is heavy hole-like. The transparency and threshold current density was 3.2 kA/cm2 and 4.1 kA/cm2, respectively at room temperature. This study provided a feasible way to fabricate CMOS compatible light sources monolithically integrated on Si platform.

Sn distribution in Ge/GeSn heterostructures formed by sputter epitaxy method

Ge/GeSn heterostructure was formed on Ge and Ge virtual substrates using the sputter epitaxy method, and the Sn profiles at the Ge/GeSn heterostructure were investigated using secondary ion mass spectrometry (SIMS). The growth temperature of the Ge/GeSn heterostructure was about 215 and 250 °C, and the thicknesses of the Ge and GeSn layers were about 90 and 70 nm, respectively. The growth rates of Ge and GeSn were relatively high and were about 0.36 and 0.4 nm/sec, respectively. The Sn content of the formed GeSn layers was estimated using an X-ray diffraction (XRD) two-dimensional reciprocal space map and was about 9 %. From the results of the atomic force microscopy and the transmission electron microscopy, the interface of the Ge/GeSn heterostructure was sharp and the surface was flat. At the Ge/GeSn interface in the sample formed at 215 °C, the Sn concentration was decreased at 3.4 nm/dec, and the 1/e decay length was about 15Å, which were smaller than 8 nm/dec and 35 Å in the previous report. The Sn diffusion depended on the growth temperature and the underlayer. The gradient of the Sn content at the 390-nm-thick GeSn layer was estimated using SIMS and was about 0.55 %/μm in the sputter epitaxy method, which was smaller than 6.2 %/μm in the previous reports. From the XRD measurements, the 390-nm-thick GeSn layer had no strain relaxation. It is considered that a high-growth rate and no strain relaxation contribute to limiting the Sn diffusion, and uniform Sn content GeSn layers were obtained.

Hydrogen-Assisted Molecular Beam Epitaxy of SiGeSn

Since its first synthesis in 2003 [1], the ternary alloy semiconductor SiGeSn has seen an increasing interest due to its unique properties in the field of Group-IV semiconductors [2–6]. SiGeSn not only allows the decoupling of its bandgap and lattice-constant by what it is predestined for the epitaxy of strain-reduced heterostructures on the Si platform. Furthermore, SiGeSn becomes a direct bandgap semiconductor at high Sn concentrations. Considering these properties, SiGeSn is an attractive material system for optoelectronic applications. An exemplary heterojunction optoelectronic device is the single confinement heterostructure laser diode, the still missing key component for the monolithic integration of the optical on-chip communication on Si.However, one of the greatest challenges faced by many Group-IV researchers is the epitaxy of SiGeSn bulk alloys with high crystal quality. The temperature induced segregation of Sn results in interstitial Sn atoms and subsequently in acceptor-like defect states, as it was already reported for GeSn [7].In this work, we show the molecular beam epitaxy (MBE) of SiGeSn structures under Hydrogen ambient. First of all, we determined the concentration of the acceptor-like defect states of undoped SiGeSn NA,defect on the basis of capacitance-voltage (C-V) measurements of SiGeSn pin diodes. Furthermore, we investigated Hydrogen-assisted epitaxy as an approach for the reduction of the acceptor-like defect states.All epitaxy experiments were performed in a 6” MBE system, where Si, Ge and Sn are used as matrix materials and B and Sb as dopants respectively. In particular, we investigated the influence of molecular (H2) as well as atomic (H) Hydrogen on the epitaxy process and therefore the quality of the grown structures. For this purpose, the MBE system was upgraded with a Hydrogen atom beam source for the generation of an atomic Hydrogen flux.Since the Sn segregation is affected mostly by the substrate temperature, this critical growth parameter is measured in-situ using an infrared pyrometer, which allows the observation of the dynamic processes on the sample surface [8] and the precise control of the substrate temperature at TSub = 200 °C during the SiGeSn epitaxy.All SiGeSn structures are based on Ge virtual substrates (Ge-VS) on Si(001) [9], followed by a 400 nm thick additional Ge buffer layer. In order to fulfil lattice matching of SiGeSn on Ge, a constant ratio of Si and Sn of Si/Sn = 3.67 was kept for all structures. The Sn concentration was varied in the range of 5 % < cSn < 10 %. For material characterization, 300 nm thick undoped SiGeSn layers were grown on this substrate layer stack (see Fig. 1a). A detailed characterization of the crystallinity and the surface roughness was performed using X-ray diffraction (XRD) and atomic force microscopy (AFM), respectively. The comparison of AFM micrographs of SiGeSn layers, grown with and without Hydrogen assistance (see Fig. 1b) show a clear reduction of the surface roughness due to Hydrogen assisted epitaxy.In order to determine NA,defect, C-V measurements on SiGeSn pin diodes (see Fig. 1c) were performed. The diode layer structure, also based on the previously described substrate layer stack, starts with a 400 nm thick p-doped SiGeSn bottom layer with an acceptor concentration of NA = 5x1019 cm-3, followed by an 300 nm thick undoped SiGeSn layer and a closing 200 nm thick n-doped SiGeSn top layer with a donor concentration of ND = 5x1019 cm-3. Subsequently, pin diodes were fabricated using a single mesa process consisting of four basic steps: Mesa structuring using inductive coupled plasma reactive ion etching (ICP-RIE) with HBr, mesa passivation with plasma enhanced chemical vapor deposition (PECVD) grown SiO2, oxide window opening using RIE with CHF3 and metallization using sputtered Al. An exemplary device can be seen in the scanning electron microscopy (SEM) image in Fig. 1d.The SiGeSn pin diodes were electrically characterised by means of C-V measurements using a Keithley 4200 semiconductor characterisation system. For further evaluation, the C-V characteristics of the pin diodes show linear behaviour when plotted on a C-2-V-scaled diagram (Fig. 1e). Under the assumption of a strongly asymmetric pn junction, (ND >> NA,defect), the slope m of the C-2-V characteristics is proportional to NA,defect. In this manner, we determined NA,defect for several SiGeSn pin diodes in dependence of the alloy composition. The results, as shown in Fig. 1f, show an acceptor-like defect concentration between 1017 cm-3 < NA,defect < 1018 cm-3, which is comparable with results reported by other groups for GeSn [7].In our presentation, we will discuss Hydrogen-assisted epitaxy as a promising approach for improving the SiGeSn crystal quality. Figure 1

(Digital Presentation) Strain Engineering of Heteroepitaxial SiGe/Ge on Si with Various Crystal Orientations

In recent years, Ge has emerged as one of the most promising materials toward next-generation high-performance and low-power-consumption optoelectronic devices. Moreover, SiGe/Ge heterostructures, consisting of strained SiGe with high Ge contents and Ge, have high potential for various applications. In terms of crystal orientations, there are various attractive choices for Ge and Ge-rich SiGe differently from Si. Particularly, the (111) orientation is very attractive for spintronics applications owing to capability of lattice matched epitaxial growth of high-quality ferromagnetic materials on the Ge(111) and SiGe(111). To create the SiGe/Ge heterostructures on the Si substrate, high quality Ge virtual substrates firstly have to be formed on the Si. The so-called Ge-on-Si is simple but very important templates for various applications, such as Ge-MOSFETs, LEDs, LDs, photo detectors, micro structures and Ge-on-Insulator (GOI) wafers etc. Especially the tensile strain induced in the Ge due to the thermal mismatch between the Ge and Si plays very important roles. For example, very efficient light emission can be obtained through strain-induced Γ-valley shift and resultant increase in the direct transition probabilities. We fabricated both Ge-on-Si(100) and Ge-on-Si(111) p-i-n LEDs and strong room-temperature EL emissions were obtained [1]. Epitaxial growth of the high quality strained SiGe on the Ge-on-Si is the most important for strain engineering of SiGe/Ge heterostrucutures. As the growth of the strained layer is limited by the critical thickness, we systematically investigated the critical thickness of the strained SiGe and clarified that it depends on the crystal orientations [2]. It was also shown that the critical thickness is markedly reduced when grown on the Ge-on-Si compared to the Ge substrate due to dislocations in the Ge-on-Si. We proposed to grow the SiGe on the Ge-on-Si on which the mesa patterning is performed. As a result, the critical thickness is drastically increased owing to the suppression of defect generation and propagation [3]. This patterning method enables us to increase the strained layer thickness and highly widen potential applicabilities of the strained SiGe/Ge heterostructures. One of the attractive applications is strained SiGe/Ge multi quantum wells (MQWs). We obtained strong roome temperature light emissions from the relatively thick MQWs formed on the Ge-on-Si (111) and Si(100) with patterning. Based on the Ge-on-Si, the larger tensile strain can be induced by the fabrication of microbridge structures, where the freestanding Ge is realized and elastic tensile stress is applied to the narrow microbridge area via the local strain relaxation of large pad areas sandwiching the bridge. In many reports, standard Si(100) substrates have been used with the bridge direction set to be <001> direction, whereas the Γ-valley shift via the tensile strain is expected to be the largest with the <111> directional uniaxial strain [4]. We attempt to fabricate the Ge microbridge along the <111> direction on the Ge-on-Si(110) substrate and very strong room-temperature PL was obtained. Moreover, when microbridge side walls are formed vertical, the generated light is well reflected by the side walls and very strong resonant light emissions are observed. Technically, the selective wet-etching of the underlying Si of the Ge-on-Si is a key process of importance to fabricate completely freestanding structures. As the crystal orientation highly affects the etching rate, a choice of the orientation is very important. Additionally, we are attempting other fabrication methods. One is making many holes in the pad areas, which enables to enhance the under-etching. Use of Ge-on-SOI or Ge-on-Insulator (GOI) substrates is another way to facilitate the under-etching as the buried oxide can be easily removed by the fast etching. Moreover, we show recent results on SiGe/Ge heterostructure imbedded microbridge, where the light emission wavelength becomes controllable and emission efficiency can be enhanced owing to the strain and band engineering.[1] K. Yamada et al. Appl. Phys. Express 14, 045504 (2021). [2] M. M. Alam, Appl. Phys. Express 12, 081005 (2019). [3] Y. Wagatsuma et al. Appl. Phys. Express 14, 025502 (2021). [4] H. Tahini et al. J. Phys. Condens. Matter 24, 195802 (2012).

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this , we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys.On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added.The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel.These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics.Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”.

Extended Carrier Lifetime in Epitaxial Ge-on-Nothing Virtual Substrates

Owing to its compatibility with mainstream Si technologies and remarkable physical properties, Ge has become a key enabler of modern semiconductor devices. In the past decades, the element has been introduced in various application areas such as high-performance and high-speed electronics, integrated photonics, photovoltaics, sensors and spintronics [1-2]. Its alloying with Si has for instance benefited the performance and power consumption of bipolar and CMOS transistors thanks to an increase in source/drain active doping concentration and channel carrier mobility. In its pure form, Ge has drawn a lot of attention for the integration of Ge nMOS devices [3-4], near-to-mid-infrared photodetectors and modulators [5-6] and as a substrate for multijunction solar cells [7], for which carrier mobility and lifetime are critical parameters.The fabrication of high-quality, scalable, relatively thin although fully relaxed Ge/Si virtual substrates (VS) is of utmost importance to enable and integrate these technologies at reduced costs. The monolithic epitaxial growth of Ge on Si however suffers from intrinsic limitations, due to the large lattice mismatch between the two materials inevitably causing the formation of a high-density network of misfit dislocations at the Ge/Si heterointerface. The inherent presence of large quantities of non-radiative recombination centers in this region has so far restricted the industrial use of Ge VS. Keeping the charge carriers away from the interface could nevertheless be in most cases an appropriate solution to contain their detrimental impact [8]. Growing thick Ge layers is a way to achieve this goal and reduce the material defectivity [9]. Unfortunately, quality improvements are limited and thicknesses exceeding 5 µm required to enter the sub 1E6 cm-2 threading dislocation density (TDD) range. This makes the process very time-consuming, expensive and induces a severe wafer bow. Another possibility consists in suppressing the defective part of the material. This can be done by splitting the Ge VS to isolate the top part of the layer from the Ge/Si interface. This method allows for performance improvements in case the replacement interface does not incur a greater penalty.In this contribution, we therefore evaluate the properties of Ge-on-nothing (GeON) suspended foils and benchmark extracted carrier lifetimes against those measured in blanket Ge/Si with different thicknesses. The concept, initially introduced by Sato et al. [10] and developed by imec to form silicon-on-nothing [11], is here applied to Ge VS, as presented in [12]. The process results in a ~ 1.2-1.4 µm thick Ge foil separated from the substrate (Figure 1) and is compared with blanket Ge VS with thicknesses ranging from 0.2 to 4.9 µm. Electron channeling contrast imaging (ECCI) and time-resolved photoluminescence (TR-PL) spectroscopy at the Ge direct bandgap are used to estimate the threading dislocation density and the free-carrier lifetime in the samples, respectively. Figure 2 and Table 1 summarize the results of this study.As expected, the estimated TDD decreases with increasing the Ge layer thickness. A minimum TDD value of ~ 4E6 cm-2 is obtained with the thicker Ge film (~ 4.9 µm thick, sample F). The GeON sample (sample D), does not stand out of the trend. On the other hand, the carrier lifetime obtained in sample D (> 30 ns) clearly outperforms those obtained for the different Ge VS (< 15 ns). This indicates that the recombination velocity at the newly formed Ge bottom surface is much lower than the one initially introduced by the defective Ge/Si interfacial region. Containing the carriers closer to this area by decreasing the thickness of the Ge VS strongly degrades their lifetime and compromises the material optical properties. We infer that GeON foils have an interesting potential for applications necessitating maximal lifetimes.

Effect of Defects on the Performance of Si-Based GeSn/Ge Mid-Infrared Phototransistors

In this paper, we discuss the impact of interfaces and defects on the frequency performance of Si-based GeSn heterojunction phototransistors (HPTs) at room temperature. Furthermore, the effect of base-emitter (B-E) voltage on the spectral responsivity (SR) and detectivity (D*) has also been studied. The presented device consists of Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> alloy in the active layer to enhance the photodetection range. However, increasing Sn content in Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> causes a lattice mismatch between Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> and Ge virtual substrate (VS), which may increase defect density at the heterointerfaces. As a result, the diffusion length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) and minority carrier lifetime (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) may decrease, thereby, degrading the performance of the device. Three major noise components such as shot noise current components at the base-emitter (B-E) and base-collector (B-C) junctions and Johnson noise have been considered for the first time to calculate the detectivity and noise-equivalent-power (NEP) of the presented device. The calculated results show that the decrease in diffusion length does not cause a significant impact on the SR, D* and internal quantum efficiency (IQE), however, it significantly degraded the cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), maximum frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ), and sensitivity (S) of the GeSn HPT at 300 K.

(Invited) Germanium-Tin Based Nano-Electronic and Photonic Devices

1. Introduction Germanium-Tin (Ge1-x Sn x ) alloy has many attractive properties that make it promising for many applications in nano-electronic and photonic devices and systems. GeSn has both higher hole and electron mobilities than Ge and Si to possibly enable scaling of the supply voltage for future high performance field-effect transistors (FETs). In addition, the tunable bandgap of GeSn by changing Sn compositions helps to extend the photo detection range beyond what can be achieved by Ge, covering wavelength larger than 1.55 µm.In this paper, we discuss the research and development of utilizing GeSn for various applications in nano-electronic and photonic devices. This includes multi-gate GeSn p-channel FETs (pFETs) on GeSn-on-insulator (GeSnOI) substrates, realization of ultra-low contact resistivity by incorporation Sn into Ge for the metal/GeSn S/D contact, and GeSn photodetectors for applications at 2 µm wavelength range. 2. GeSn pFinFETs with Sub-10 nm Fin Width on GeSnOI Substrates Large-area GeSnOI substrates were fabricated using direct wafer bonding (DWB) and layer transfer techniques at a 200 mm wafer scale [1]. This GeSnOI substrate, together with the multi-gate architecture, enabled the realization of high performance Ge1-x Sn x p-FETs with ultra-scaled channel length down to 50 nm [2]. An optimized try etch process was developed to fabricate GeSn FinFETs with fin width less than 10 nm. Excellent electrical characteristics were achieved with subthreshold swing of 63 mV/decade, intrinsic transconductance of 900 µS/µm at VDS of -0.5 V, and high-field effective mobility of 275 cm2/V·s. 3. Metal/ GeSn p-type Contact with Ultra-low Contact Resistivity. GeSn has a smaller hole Schottky barrier and a hole effective mass (mh ) as compared to Ge. These advantages make GeSn attractive for low-resistance p-type contacts. In-situ Ga doping was introduced during the epitaxial growth of GeSn using molecular-beam epitaxy (MBE) and more than 50% reduction of specific contact resistivity ρc has been observed by incorporation of 5% Sn into Ge [3]. Further optimization of GeSn doping process by surface segregation or cold implantation reduces ρc of Ti/p+-GeSn to sub-10-9 Ω-cm2 regime [4]. The ultra-low ρc of Ti/p+-GeSn is retained after anneal at 420 oC for 1 hour, showing adequate thermal stability for BEOL process in current CMOS technology [5]. 4. GeSn Photo-detectors for Applications at 2 µm Wavelength Range High-speed photo detection was demonstrated beyond traditional telecommunication bands and reaching at 2 μm band, realized by GeSn/Ge multiple-quantum-well (MQW) photodiode on Si substrate [6]. GeSn/Ge MQW structure was employed to increase the critical thickness (hc ) of epitaxial GeSn on Ge virtual substrate. A decent responsivity of 15 mA/W was obtained at 2 μm. A low leakage current density of 44 mA/cm2 was achieved at reverse bias of 1 V, which is among the lowest reported values for all GeSn photodiodes. A 3-dB bandwidth (f 3-dB) larger than 10 GHz was experimentally demonstrated directly at 2 μm. Acknowledgment We would like to acknowledge the funding support from Singapore Ministry of Education Tier 2 grants (R-MOE2018-T2-1-137 and MOE2018-T2-2-154).[1] D. Lei et al., Appl. Phys. Lett., 109, 022106, 2016.[2] D. Lei et al., VLSI Symposia, 2018, 197-198.[3] Y. Wu et al., J. Appl. Phys., 122, 224503, 2017.[4] Y. Wu et al., VLSI Symposia, 2018, 77-78.[5] Y. Wu et al., IEEE Electron Device Lett., 40, 1575-1578, 2019.[6] S. Xu et al., IEDM, 2018, 544-547.

Capacitance-Voltage Measurements on MBE-Grown Ge-SixGe1-x-ySny Heterojunction pn-Diodes for Material Characterisation

In recent years, there has been an increased interest in the ternary Group-IV semiconductor alloy SixGe1-x-ySny [1–4]. Since it allows the decoupling of its bandgap and its lattice-constant, SixGe1-x-ySny is predestined for the realisation of lattice-matched heterojunctions on Ge(Sn) virtual substrates on the Si platform. Furthermore, SixGe1-x-ySny is a predicted direct bandgap semiconductor at higher Sn concentrations, which makes it attractive for optoelectronic applications. An exemplary heterojunction optoelectronic device would be the single confinement heterostructure laser diode, the still missing key component for the monolithic integration of the optical on-chip communication on Si.However, the design and dimensioning of heterojunction devices requires detailed knowledge of the electrical properties of the alloy semiconductor over composition, where currently much less is known about SixGe1-x-ySny. Although, previous investigations have focused mostly on the growth conditions and the optical properties of SixGe1-x-ySny bulk alloys [1,2,4].In this work, we will concentrate on the growth and electrical characterisation of Ge-SixGe1-x-ySny heterojunction diodes. In detail, we will highlight the possibilities of current-voltage (I-V) and capacitance-voltage (C-V) measurements on Ge-SixGe1-x-ySny heterojunction pn-diodes as a useful tool for material characterisation. For this purpose, we grew a series of four samples with different composition of the SixGe1-x-ySny layer, but the SixGe1-x-ySny composition fulfilling lattice-matching on Ge (see Fig 1 (a)). Afterwards, we fabricated single mesa diodes to enable the subsequent electrical characterisation of the grown heterostructure diodes.The growth process was performed in a 6” molecular beam epitaxy (MBE) system, where Si, Ge and Sn are used as matrix materials and B and Sb as dopants, respectively. Since the condition of lattice matched growth of SixGe1-x-ySny requires a fixed ratio of Si/Sn = 3.66, the Si and Sn fluxes were kept constant for all samples. Thus, we varied the Ge flux to achieve different SixGe1-x-ySny compositions, resulting in a varying SixGe1-x-ySny growth rate. This method enables better control of the lattice matching but also requires a highly precise calibration of the evaporation cells of the alloy compound fluxes. The Sn concentration of the SixGe1-x-ySny layers was varied between 5 % and 12.5 %. Since the most critical growth parameter is the substrate temperature, it is therefore measured and controlled in-situ by a thermocouple as well as an infrared pyrometer. Especially, the infrared pyrometer allows us to observe the dynamic processes on the sample surface during growth. For the growth of the SixGe1-x-ySny layer, we chose to keep the substrate temperature at TSub = 200 °C, which is mainly based on our previous SixGe1-x-ySny growth studies.The heterojunction pn-diode (see Fig 1 (a)) is formed by a p-doped Ge layer with an acceptor concentration of NA = 1018 cm-3 and the n-doped SixGe1-x-ySny layer with a donor concentration of ND = 5·1019 cm-3. In order to achieve a good ohmic contact to the p-Ge, a highly p-doped Ge layer forms the underlying bottom contact of the diode. The whole diode structure is grown on our standard Ge virtual substrate (VS) on Si(100) [5].A detailed material characterisation was performed to achieve information of the composition as well as the crystal quality using X-ray diffraction (XRD) and Raman spectroscopy.After MBE growth, the samples were processed to diodes in a single mesa process. For the subsequent I-V and C-V measurements, we used a Keithley 4200 semiconductor characterisation system using the bottom as signal and the top as ground contact (Fig 1 (b)). For the C-V measurements, a parallel capacitance (C) and conductance (G) model was applied. The maximum measurement frequency was f = 100 kHz. Fig. 1 (c) shows a comparison of the current density-voltage (J-V) characteristics of diodes with a mesa radius of 80 µm for all four compositions. As can be seen, good diode behaviour is achieved even for high Sn concentrations. An exemplary capacitance-voltage and conductance-voltage (C-V and G-V) characteristics of the sample with 10 % Sn is shown in Fig 1 (d). The C-V characteristics shows good agreement with the theoretical curve in the range of -0.6 V ≤ vDC ≤ 0 V. Further calculations in this range allowed us the extraction of the built-in-voltage of the heterojunction diode, an important parameter of a pn-heterojunction. We present detailed results of the C-V measurements of our diodes and the applied methods for material characterisation.Our results show that C-V measurement of SixGe1-x-ySny heterojunction pn-diodes is a useful tool for the determination of electrical parameters of this novel ternary alloy semiconductor SixGe1-x-ySny. These parameters are crucial for the further design of SixGe1-x-ySny heterojunction devices. Figure 1

Epitaxial Ge-on-Nothing Virtual Substrates for 3D Device Stacking Technologies

Future monolithic heterogeneous integration of Ge and IIIV materials in electronic, optoelectronic and photonic devices requires advanced layer transfer and 3D device stacking technologies, which starts with the fabrication of suitable (virtual) substrates. A layer transfer process based on the reorganization of macro-porous Si at high temperature was developed by imec [1]. The developed fabrication scheme to fabricate macropores is based on standard UV lithography and dry etching techniques rather than electrochemical etching. This enables an easy transfer to full Si wafers (up to 300 mm). During a high-temperature step, the top part of the macro-porous Si reflows. By using proper anneal conditions, the layer detaches from the mother substrate, being anchored by a few attachment points only, forming a ‘Si on nothing’ (SoN) stack (Fig. 1a). The suspended Si layer can then easily be transferred to another substrate.In this contribution, we assess the suitability of macro-porous Si and SoN as starting material for Ge virtual substrates. The goal is to provide a fabrication scheme that allows an easy detachment of the virtual substrate after wafer to wafer bonding. Macro-porous Si was only fabricated in the inner 10x10 cm2 area of 200 mm wafers using imec’s qualified fabrication scheme. Ge layers were simultaneously grown on the inner macro-porous Si (or SoN) and the outer bulk Si. This allows to compare the material properties without the risk of wafer to wafer variations due to non-reproducibility issues. Our approach for making macro-porous Si and SoN provides mono-crystalline, nearly defect-free, and extremely smooth Si starting surfaces. A standard low temperature epitaxial Ge growth process in an ASM-Epsilon® 2000 system was used to deposit the Ge layers [2].As an example, Fig. 1b shows a 1.25 mm thick mono-crystalline epitaxial Ge layer grown on a macro-porous Si layer. The Ge growth proceeds in a 2-dimensional mono-crystalline growth mode. The surface morphology of the grown Ge is not affected by the starting surface (Fig. 1c,d). The Full Width at Half Maximum (FWHM) as extracted from w-2q High Resolution X-ray Diffraction scans acquired around the Ge (004) Bragg peak is strongly reduced after a post Ge deposition anneal, which was also reported for Ge on bulk Si [2]. Threading dislocations annihilate during the post-epi anneal. FWHM values as low as 160 arc sec have been measured for 1.25 mm thick Ge layers independent of the underlying layer. This reflects the high material quality of the grown Ge. The difference in thermal expansion coefficient between Si and Ge results in some tensile stress in the annealed Ge layer, which explains the well-known shift in XRD peak position. The improvement in material quality by using a post-epi anneal is also reflected in the carrier lifetime as extracted from room-temperature photoluminescence measurements. The carrier lifetime increases from <0.2 ns (as-grown layers) to 3.3 ns and 3.6 ns for Ge on porous Si and bulk Si, respectively. The TDD, as extracted from ECCI measurements, was identical for both parts of the Si wafer (2-4e7 cm-2) and close to the values expected from literature. The material properties listed above are not affected by the thickness of the closed Si layer in-between the Ge and the porous Si.In conclusion, we developed a fabrication scheme for strain-relaxed Ge grown on SoN (or on macroporous Si) starting from conventional Si substrates. The material properties of the virtual Ge substrate are identical to those obtained for Ge grown on bulk Si. The virtual substrate serves as starting material for layer transfer and 3D device stacking technologies. The fabrication scheme can be extended to (defect free) bulk Ge for which the fabrication of Ge on nothing followed by layer transfer has been demonstrated [3].

Epitaxial Ge-on-Nothing Virtual Substrates for 3D Device Stacking Technologies

We introduce a fabrication scheme for strain-relaxed Ge, epitaxially grown on a Si-on-Nothing (SiON) template formed from macro-porous Si. The SiON template is fabricated on regular Si substrates using conventional lithography, dry-etching and annealing routines. The material properties of the virtual Ge substrate grown on this detachable template are identical to those obtained for Ge grown on bulk Si. Strain-relaxed, suspended, and detachable Ge-on-Nothing (GeON) was fabricated using a similar fabrication scheme except for the epitaxial growth of Ge on Si, which was performed before the patterning of the substrate. For GeON, the extracted excess carrier lifetime using time-resolved photoluminescence (32 ns) was > 4 times higher than the values measured for Ge grown on bulk Si with a similar thickness of the Ge layer. Both templates can be considered as starting material for layer transfer and 3D device stacking technologies provided that successful detachment from the parent substrate can be demonstrated.

(Invited) Heteroepitaxy and Strain Engineering of Germanium-Silicon-Tin Ternary Alloy Semiconductor Thin Films for Energy Band Design

Strain engineering of group-IV semiconductor thin film is a key for energy band design and engineering for electronic and optoelectronic applications. In this paper, we report our recent achievements for strain relaxation method of Ge1 −x−y Si x Sn y ternary alloy semiconductor epitaxial layer on various substrates. Virtual Ge substrate effectively enhances the strain relaxation of Ge1 −x−y Si x Sn y layer and also improves the surface morphology and uniformity after the strain relaxation. Ion implantation into Ge substrate is also effective to enhance the strain relaxation and achieves a large in-plane lattice constant as a buffer layer for the growth of strain-relaxed Ge1 −x Sn x epitaxial layer with a Sn content as high as 10%.

Reduced Lasing Thresholds in GeSn Microdisk Cavities with Defect Management of the Optically Active Region

GeSn alloys are nowadays considered as the most promising materials to build Group IV laser sources on silicon (Si) in a full complementary metal oxide semiconductor-compatible approach. Recent GeSn laser developments rely on increasing the band structure directness, by increasing the Sn content in thick GeSn layers grown on germanium (Ge) virtual substrates (VS) on Si. These lasers nonetheless suffer from a lack of defect management and from high threshold densities. In this work we examine the lasing characteristics of GeSn alloys with Sn contents ranging from 7 \% to 10.5 \%. The GeSn layers were patterned into suspended microdisk cavities with different diameters in the 4-\SI{8 }{\micro\meter} range. We evidence direct band gap in GeSn with 7 \% of Sn and lasing at 2-\SI{2.3 }{\micro\meter} wavelength under optical injection with reproducible lasing thresholds around \SI{10 }{\kilo\watt\per\square\centi\meter}, lower by one order of magnitude as compared to the literature. These results were obtained after the removal of the dense array of misfit dislocations in the active region of the GeSn microdisk cavities. The results offer new perspectives for future designs of GeSn-based laser sources.

Lattice Vibrational Modes in Epitaxial Metastable Germanium-Tin Semiconductors

Group IV semiconductors, such as GeSn and SiGeSn, are of growing interest for silicon-compatible electronic and photonic applications, notably due to the possibility of tuning the bandgap directness and energy to cover a broad range from the short-wave infrared (SWIR) to the mid-infrared (MIR) [1]. While germanium is an indirect-bandgap semiconductor, an indirect-to-direct transition in GeSn alloys is expected for Sn incorporation higher than 9%, but the residual compressive strain typical to epitaxial layers increases the concentration of Sn to obtain a direct-bandgap [2]. Therefore, an understanding of the interplay of strain and composition on the band structure of GeSn semiconductors is of compelling importance in order to precisely control their physical properties. This calls for accurate analysis of the as-grown material properties and its correlation with the measured optical and electrical performance. Raman spectroscopy is a non-destructive method commonly used to assess the role of the effects of composition and strain in shaping the lattice vibrations. The use of a 633 nm excitation enables a clear detection of all Raman modes in GeSn layers independently of their composition, comparatively to the more restricted results associated with the use of 488 nm[3] or 532 nm [4] excitation. This is plausibly attributed to the fact that this wavelength might be close to resonance with the alloy’s E1 gap [5]. There are very few reports on the identification of the Ge-Sn mode [6] and the disorder-activated mode coinciding with the maximum in the one-phonon density of states in Ge [7], but quantitative analyses of the effects of composition and strain on these modes remain conspicuously missing in literature.With this perspective, this work presents a detailed study of Raman vibrational modes in Sn-rich GeSn semiconductors and how their behavior is affected by temperature. The use of samples of various degrees of Sn composition and in-plane compressive strain allows the decoupling of these effects on the Ge-Ge, DA and Ge-Sn vibrational modes, thus providing an effective platform to test the current predictive models. Samples were grown in a chemical vapor deposition (CVD) reactor using monogermane (GeH4) and tin-tetrachloride (SnCl4) precursors [8]. The GeSn multi-layer heterostuctures with a Sn content in the 4-16 at.% range were grown on a Ge virtual substrate (VS) on a Si wafer. Using X-ray diffraction (XRD), reciprocal space mappings (RSM) were performed on all samples to retrieve the Sn composition and the strain. Temperature-dependent Raman measurements were performed from room temperature (300K) and down to 77 K.In GeSn, the asymmetrical profile of the observed Raman modes is due to alloying as substitutional Sn atoms break the translational symmetry and lead to a relaxation of the momentum selection rule [9]. Therefore, the use of exponentially modified gaussian functions (EMG) as a fitting curve can reflect the asymmetrical profile of the different analyzed Raman modes with much better accuracy [10]. The measurement temperature has a clear effect on the fitting parameters, such as the integrated area of the peak , the full width at half maximum (FWHM), the asymmetry, and its position. For example, the Ge-Sn and Ge-Ge peaks increase in wavenumber with decreasing temperature, while the DA peak shows the opposite trend. Ongoing work focuses on establishing the behavior of the characteristics of each mode. Based on these detailed Raman studies, an exhaustive discussion of the influence of temperature, lattice strain and Sn content on GeSn vibrational modes will be presented. Acknowledgements The authors thank J. Bouchard for the technical support, and NSERC Canada (Discovery, SPG, and CRD Grants), Canada Research Chairs, Canada Foundation for Innovation, Mitacs. Reference [1] S. Gupta, et al., J. Appl. Phys. 113, 7 (2013).[2] A. Attiaoui and O. Moutanabbir, J. Appl. Phys., 116, 6 (2014).[3] R. R. Lieten et al., ECS J. Solid State Sci. Technol., 3, 12, pp. P403–P408 (2014).[4] A. Gassenq et al., Appl. Phys. Lett., 110, 11, p. 112101 (2017).[5] R. Chen et al., ECS J. Solid State Sci. Technol., 2, 4, pp. P138–P145 (2013).[6] D. Zhang et al., J. Alloys Compd., 684, pp. 643–648 (2016).[7] V. D’Costa et al., Solid State Communications, 144, 5-6, pp. 240-244 (2007).[8] S. Assali, J. Nicolas and O. Moutanabbir, Journal of Applied Physics, 125, 2, p. 025304 (2019).[9] P. Parayanthal and F. H. Pollak, Phys. Rev. Lett., 52, 20, pp. 1822–1825 (1984).[10] É. Bouthillier et al., “Decoupling the effects of composition and strain on the vibrational modes of GeSn”, https://arxiv.org/abs/1901.00436, 2019.

Growth and Characterisation of Pure B Layers on Ge(hkl) and Si(hkl) Utilizing Molecular Beam Epitaxy

Since the first investigations on pure B layers on Si have shown their potential application in high performance electronic devices, the interest in these structures increased rapidly. In this study, we report the growth of pure B layers on Ge(001), Si(001) and Si(111) substrates as well as on virtual Ge(100) substrates on Si utilizing molecular beam epitaxy in order to form ultra-shallow pn-junctions. A complementary metal oxide semiconductor compatible fabrication process was used afterwards to fabricate single mesa diodes. Further electrical characterizations of the devices show diode behavior with high ideality, low series resistance and low dark current density, compared to Schottky and homogenous doped diodes. Concluding the given results, we discuss further research key aspects and possible applications of this novel material.