Ge PAI Research Articles

Investigation of Ultrathin Ni Germanosilicide for Advanced pMOS Contact Metallization

Ultrathin Ni germanosilicide liner ( x Ge y /p+-SiGe:B contacts show improved specific contact resistivity ( $\rho _{\text {c}}$ ) with respect to conventional TiSi x Ge y /p+-SiGe:B ones. It is further demonstrated that the $\rho _{\text {c}}$ of NiSi x Ge y /p+-SiGe:B contacts is correlated with both Ni thickness and post metal anneal (PMA). Utilizing Ge preamorphization implant (Ge PAI) followed by B ion implant (B I/I), the active concentration of B dopants is enhanced from $1\times 10^{{20}}$ cm $^{-{3}}$ for reference to $6\times 10^{{20}}$ cm $^{-{3}}$ . Consequently, a remarkably lowered $\rho _{\text {c}}$ of $\sim 7.42\times 10^{-{9}} \,\Omega \cdot $ cm2 is achieved for NiSi x Ge y /p+-SiGe:B contacts, where Ni layer is 20 A and PMA temperature is 500 °C.

Impact of Ge pre-amorphization implantation on Co/Co-Ti/n+-Si contacts in advanced Co interconnects

Co has been proposed as one of the most promising candidates to replace W or Cu in interconnects, where Co–Ti could be used as a single barrier/liner to prevent Co out-diffusion into dielectric and Si substrate as well as to enhance the adhesion property. In this paper, the material and electrical properties of Co/Co-Ti/n+-Si contacts with different compositions and thicknesses of Co–Ti, with and without Ge pre-amorphization implantation (Ge PAI) were investigated elaborately. Sheet resistance, phase formation, interfacial morphology and element distribution were comprehensively characterized in terms of four-point probe, X-ray diffraction and high-resolution transmission electron microscopy in combination with corresponding energy dispersive X-ray spectroscopy respectively. Meanwhile, the specific contact resistivity (ρc) was extracted using refined transmission line model structures, and it is found that Ge PAI is indeed beneficial in reducing ρc values in Co/Co-Ti/n+-Si contacts. With the assistance of Ge PAI, the lowest ρc value of 8.56 × 10−9 Ω cm2 is accomplished for Co/Co0.65Ti0.35/n+-Si contacts, which is a ∼47.8% reduction in contrast to that without Ge PAI.

Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40 μA/μm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with V DS = V GS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressed at the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decade was obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.

Effects of 72Ge/74Ge preamorphization combined with sub-keV boron implantation in pMOSFET fabrication

The reduction of transient enhanced diffusion (TED) and suppression of short-channel effect (SCE) are very critical for the formation of ultra shallow junctions required for deep sub-micron devices. This article reports the nanoscale gate length of p-type metal–oxide-semiconductor field-effect transistor (pMOSFET) technology using 72Ge/74Ge germanium preamorphization implantation (Ge PAI) upon the (100)-oriented silicon substrates. It is demonstrated that the channeling can be eliminated by the formation of a Ge-implantation induced thin amorphous layer near the surface prior to boron implantation. Optimizing the amorphous layer thickness by controlling a high 72Ge/74Ge ratio, the device performance of pMOSFETs can be enhanced. In addition, the optimum conditions of Ge PAI would help the confinement of boron ions to avoid the channeling phenomenon. It is also found that the thin Ge PAI amorphous layer formed by a low 72Ge/74Ge ratio would cause the degradation of threshold voltage (Vth) roll-off characteristics, Ion/Ioff ratio and the fluctuation of 62.14% in gain factor, as compared to that formed by a high 72Ge/74Ge ratio. It is attributed to a thinner Ge amorphous layer that has a weak ability to suppress the channeling tail of boron, as compared to a thicker Ge amorphous layer at the same implanted doses and acceleration energies among various 72Ge/74Ge ratios.

Suppressing ability of germanium preamorphisation thicknesses combined with sub-keV boron implantation for drive current improvement

The nanoscale gate length of CMOS technology using germanium preamorphisation implantation (Ge PAI) is reported. By optimising the Ge PAI dose and amorphous thickness, the device characteristics can be enhanced and the fluctuations can be minimised. Optimum conditions of Ge PAI can also minimise the transient enhanced diffusion of boron by reducing the density of point defects generated by boron implants. Suppressing ability is related to the Ge amorphous layer thickness, which can be varied with the concentration ratio of 72 Ge to 74 Ge PAI doses. It is attributed to a gradated and thinner Ge amorphous layer to have a weak ability to suppress the channelling tail of boron than a uniform and thicker Ge amorphous layer at the same implanted dose.

Atomistic modelling for boron diffusion profile in silicon posterior to germanium pre-amorphization

In this paper, the physics of the retardation of boron diffusion in a germanium pre-amorphized (Ge PAI) silicon substrate is reported through the kinetic Monte Carlo (KMC) approach. In order to investigate the mechanism of the retardation of boron diffusion for Ge PAI silicon, the temporal behaviour of self-interstitials as well as the evolution of various kinds of boron clusters is calculated via a fine time-scale KMC calculation. Our KMC study reveals that both interstitials and vacancies in the germanium pre-amorphized area disappear very rapidly, followed by retardation of boron diffusion due to the presence of excessive interstitials in the end of range (EOR). Furthermore, we observed that more amount of boron clusters is produced in Ge PAI silicon than the silicon with no PAI. This seems to be due to interstitials arriving from the EOR band generated by the germanium implant.

Junction and Profile Analysis using Carrier Illumination

AbstractCarrier Illumination™ (CI) is an optical technique for non-destructive in-line monitoring of post-anneal junction depth and pre-anneal PAI depth and dose with wafer mapping capabilities. This work intends to extend the use of the CI-measurements from a range-specific quantitative measurement towards a more universal quantitative analysis of junction depth, profile abruptness and implant dose. For that purpose this paper presents a systematic study of the CI response to a wide variety of post anneal implant processes, varying parameters including implant species, dose and energy, annealing condition, and surface preparation.Samples containing B, BF2 and As-implants with and without Ge PAI layers, with junction depths between 10-120 nm, were measured. In addition near-ideal box-like profiles (as obtained with CVD-growth) were fabricated and measured. For the abrupt CVD profiles, CI measures the junction position with sub-nm resolution independent of the CI-analysis conditions. For more graded profiles resulting from annealed implants, the correlation to the SIMS junction depth becomes a function of generation laser current (which is proportional to the applied power). As the concentration level, at which the correlation is made, can be adjusted over a concentration range of approximately 2x1018 to 2x1019/cm3 by changing the laser current, a route towards correlating the CI measurement with profile abruptness becomes feasible.

Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-μm pMOSFET's

Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-/spl mu/m pMOSFET's. The parasitic resistance in p/sup +/ S/D extension region increases remarkably by decreasing BF/sub 2/ ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p/sup +/ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p/sup +/ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF/sub 2/ and the amorphization rate of substrate. Therefore, in sub-0.25-/spl mu/m era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p/sup +/ extension of 0.15 /spl mu/m pMOSFET's. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%.