Ge Metal Oxide Semiconductor Field Effect Transistors Research Articles

Enhanced zirconia oxide dielectric quality of germanium p-channel metal oxide semiconductor field effect transistor by in-situ low temperature treatment in atomic layer deposition process

The gate dielectric quality of germanium (Ge) p-channel metal oxide semiconductor field effect transistor (MOSFET) is enhanced by using an in-situ low temperature treatment in atomic layer deposition (ALD) process in this work. With additional oxygen flow or remote oxygen-based plasma, the dangling bond, oxygen vacancy, and oxide traps in the ALD-formed zirconia oxide gate dielectric can be effectively passivated. Unlike the traditional post deposition annealing process that generally causes an increased equivalent oxide thickness (EOT) significantly, the in-situ low temperature treatment can lower the EOT value, reduce the gate leakage current, and improve the gate dielectric quality at the same time. As a result, the sample with an additional oxygen gas flow can exhibit a lower hysteresis value, better frequency dispersion characteristics, higher on/off current ratio, lower sub-threshold swing value, higher transconductance value, higher field effect mobility value, and better uniformity, simultaneously. This dielectric quality enhancement technique with in-situ low temperature process is promising to overcome the trade-off between EOT and gate leakage for the future Ge MOSFET devices.

Reduction of Slow Trap Density in Al2O3/GeO x N y /n-Ge MOS Interfaces by PPN-PPO Process

The realization of high- ${k}$ /IL/Ge MOS interfaces with thin equivalent oxide thickness (EOT), low interface state density ( $\text{D}_{{\text {it}}}$ ), and high reliability is strongly needed for realizing Ge metal–oxide–semiconductor field-effect transistors (MOSFETs). In this article, we examine the properties of the slow trap areal density ( $\Delta \text{N}_{{\text {st}}}$ ) and $\text{D}_{{\text {it}}}$ in Al2O3/GeOxN y /n-Ge MOS interfaces formed by atomic layer deposition (ALD) Al2O3 films with plasma post nitridation (PPN) and plasma post oxidation (PPO). Here, the process order and process time of PPN and PPO are systematically changed to optimize the Al2O3/GeO x N y /n-Ge MOS interface properties. It is found that N atoms induced into GeO x can suppress slow electron trapping. An Al2O3/n-Ge structure with 1-min PPN before PPO can reduce $\Delta \text{N}_{{\text {st}}}$ by 34% in a weak electric field, whereas PPN after PPO increase $\Delta \text{N}_{{\text {st}}}$ . Also, the sufficient time PPO process after PPN can decrease $\text{D}_{{\text {it}}}$ to a similar level as that at the Al2O3/GeO x /n-Ge MOS interfaces. The temperature dependence of electron trapping properties is also experimentally evaluated. The slow electron trapping is expected to be more suppressed for the GeO x N y interfaces at real device operation temperature.

Quantitative evaluation of slow traps near Ge MOS interfaces by using time response of MOS capacitance

Time-dependent changes in current and threshold voltage due to slow traps near Ge metal–oxide–semiconductor (MOS) interfaces is one of the most serious problems in Ge metal–oxide–semiconductor field-effect transistors (MOSFETs). In this study, we propose a new evaluation method of slow traps near MOS interfaces utilizing the time response of capacitance in MOS capacitors at a constant gate voltage, allowing us to evaluate the density and time constant of slow traps. We apply this method to Au/Al2O3/GeOx/Ge MOS capacitors and evaluate the density and average time constant of slow traps. The slow trap density of n-Ge MOS capacitors is found to be much larger than that of p-Ge MOS capacitors, indicating that a higher density of slow traps exists near the conduction band edge. We also examine the effects of post deposition annealing in a variety of ambient gases, including several hydrogen-based species, on the properties of slow traps.

Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation). It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET) device.

Capacitance Characteristic Optimization of Germanium MOSFETs with Aluminum Oxide by Using a Semiconductor-Device-Simulation-Based Multi-Objective Evolutionary Algorithm Method

This paper, for the first time, optimizes the characteristics of capacitance–voltage (C–V) of germanium (Ge) metal-oxide-semiconductor field effect transistors (MOSFETs) with aluminum oxide (Al2O3) by using a semiconductor-device-simulation-based multi-objective evolutionary algorithm (MOEA) technique. By solving a set of 2D semiconductor device transport equations, numerical simulation is intensively performed for the optimization of the C–V curve of Ge MOSFET devices. To optimize the capacitance of Ge MOSFETs with respect to the applied voltage, by minimizing the total errors of the C–V curve between the device simulation and a given specification (and experimentally measured data), the thicknesses of Al2O3 and GeO2, the work function of gate electrodes, the distribution range of channel doping, the dielectric constants of Al2O3 and GeO2, and the source/drain doping concentration are considered in the process of optimization. The semiconductor device simulation and the MOEA method are integrated and performed based on a unified optimization framework. According to the sharp variation characteristics of the C–V curve, except for using a residual sum of squares (RSS) (i.e., the sum of squares of residuals) as an objective function, physical key parts of the curve are also considered in the optimization problem. The engineering results of this study indicate that the semiconductor-device-simulation-based MOEA method shows great performance to optimize the parameters, which not only minimize the objective values but also match the curve shape.

III-V/Ge Device Engineering for CMOS Photonics

Heterogeneous integration of III-V compound semiconductors and Ge on the Si platform is one of the promising technologies for enhancing the performance of metal-oxide-semiconductor field effect transistors (MOSFETs) beyond the 10-nm technology node because of their high carrier mobilities. In addition, the III-Vs and Ge are also promising materials for photonic devices. Thus, we have investigated III-V/Ge device engineering for CMOS photonics, enabling monolithic integration of high-performance III-V/Ge CMOS transistors and III-V/Ge photonics on Si. The direct wafer bonding of III-V on Si has been investigated to form III-V on Insulator for III-V CMOS photonics. Extremely-thin-body InGaAs MOSFETs with the gate length of approximately 55 nm have successfully been demonstrated by using the wafer bonding. InP-based photonic-wire waveguide devices including micro bends, arrayed waveguide gratings, grating couplers, optical switches, and InGaAs photodetectors have also been demonstrated on the III-V-OI wafer. The gate stack formation on Ge is one of the critical issues for Ge MOSFETs. Recently, we have successfully demonstrated high-quality GeOx/Ge MOS interfaces formed by thermal oxidation and plasma oxidation. High-performance Ge pMOSFET and nMOSFET with thin EOT have been obtained using the GeOx/Ge MOS interfaces. We have also demonstrated that GeOx surface passivation is effective to reduce the dark current of Ge photodetectors in conjunction with gas-phase doped junction. We have also investigated strained SiGe optical modulators. We expect that compressive strain in SiGe enhances modulation efficiency, and an extremely small VπL of 0.033 V-cm is predicted. III-V/Ge heterogeneous integration is one of the promising ways for achieving ultrahigh performance electronic-photonic integrated circuits.

(Invited) GOI Substrates: Fabrication and Characterization

Wafer bonding is an attractive process to creat new structures and materials, alternative to conventional bulk-Si substrates, in the form of substrates for the advanced metal-oxide-semiconductor field effect transistors (MOSFETs). A germanium on insulator (GOI) substrate attracts much attention because it makes the best use of the higher carrier mobility advantages compared with Si, and is suitable to further downscaling of Ge MOSFET dimensions. However, careful consideration is given especially to the bonded interface between Ge and buried oxide, which should have a device grade quality. In this work, we fabricate GOI substrates by using a wafer bonding method. Atomic structures, chemistry, and electrical properties of the Ge/BOX interface are also characterized.

High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation

An ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al2O3 layer between HfO2 and Ge for suppressing HfO2-GeOx intermixing, resulting in a low-interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the Dit in 1011 cm-2·eV-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm2/V·s and peak electron mobilities of 754 and 689 cm2/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO2/Al2O3/GeOx/Ge gate stacks.

Variation of Surface Roughness on Ge Substrate by Cleaning in Deionized Water and its Influence on Electrical Properties in Ge Metal–Oxide–Semiconductor Field-Effect Transistors

The control of Ge surface roughness using deionized water (DIW) was systematically investigated. It was found that a very flat surface was obtained by pure-DIW dipping at room temperature, while quite a rough surface was observed at high temperature. The surface reaction model of Ge with H2O is proposed to explain the correlation of surface roughness (SR) formation with the etching process of Ge in DIW. In addition, the effects of SR on electrical properties in Ge/GeO2 stack such as capacitance–voltage (C–V) curves, interface state density, and electron mobility are presented.

Variation of Surface Roughness on Ge Substrate by Cleaning in Deionized Water and its Influence on Electrical Properties in Ge Metal–Oxide–Semiconductor Field-Effect Transistors

Variation of Surface Roughness on Ge Substrate by Cleaning in Deionized Water and its Influence on Electrical Properties in Ge Metal–Oxide–Semiconductor Field-Effect Transistors

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors

In this paper, the thermal stability of Ni-germanide is improved by utilizing Ni/Co/Ni/TiN structure for Ge metal–oxide–semiconductor field effect transistors (MOSFETs) technology. It was shown that the Ni/Co/Ni/TiN structure improved the thermal stability of Ni-germanide mainly due to the suppression of Ni diffusion, and/or the retardation of agglomeration. The incorporated Co atoms distributed, mainly in the top region of the Ni-germanide and it is believed that this Co-rich Ni-germanide layer in the upper region of Ni-germanide enhanced the thermal stability. Therefore, the proposed Ni/Co/Ni/TiN structure is promising for the formation of a highly thermally immune Ni-germanide for nanoscale Ge MOSFETs technology.

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors

Optimization of Germanium (Ge) $\hbox{n}^{+}/\hbox{p}$ and $\hbox{p}^{+}/\hbox{n}$ Junction Diodes and Sub 380 $^{\circ}\hbox{C}$ Ge CMOS Technology for Monolithic Three-Dimensional Integration

In this paper, we optimize and investigate Ge n+/p and p+/n junction diodes formed by Co metal-induced dopant activation technique at the activation temperature range between 300 °C and 420 °C in terms of on/ off-current ratio. Combining this low-temperature n+/p and p+/n junction formation technique with a low-temperature gate stack comprised of Al/Al2O3/GeO2 by ozone oxidation technique, we demonstrate n- and p-channel Ge metal-oxide-semiconductor field-effect transistors (MOSFETs), respectively, at sub-360 °C and 380 °C. This low-temperature Ge MOSFET process can be utilized to integrate Ge complementary metal-oxide-semiconductor devices above interconnect layers for monolithic 3-D integrated circuits.

N-Channel Germanium MOSFET Fabricated Below 360 <formula formulatype="inline"><tex Notation="TeX">$^{ \circ}\hbox{C}$</tex></formula> by Cobalt-Induced Dopant Activation for Monolithic Three-Dimensional-ICs

Below 360°C, we demonstrate germanium (Ge) n+/p junction diode and n-channel Ge metal-oxide-semiconductor field-effect transistor (MOSFET) with a low temperature Al/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stack for monolithic 3-D integration using a metal-induced dopant activation (MIDA) technique. In particular, the cobalt (Co) MIDA phenomenon is investigated on Ge damaged by an implantation process. Shallow (~100 nm) source/drain junctions with very low resistivity (5.2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> Ω-cm) are then achieved at very low temperature by the Co MIDA technique. Consequently, high diode and transistor current on/off ratios (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> and ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , respectively) are obtained in this n-channel Ge MOSFET.

Gas Phase Doping of Arsenic into (100), (110), and (111) Germanium Substrates Using a Metal–Organic Source

The gas phase doping of arsenic (As) into (100), (110), and (111) germanium (Ge) substrates at 500 to 700 °C using a metal–organic vapor phase epitaxy (MOVPE) system with tertiarybutylarsine (TBAs) as the As source was investigated for the n-type source/drain formation of Ge metal–oxide–semiconductor field effect transistors (MOSFETs). The surface concentration of As analyzed by secondary ion mass spectroscopy (SIMS) was approximately 1×1019 cm-3 and the diffusion constant was one order of magnitude smaller than that of As induced by ion implantation at 700 °C. The diffusion constant was linearly dependent on the As concentration, and the activation energy and pre-exponential factor of the As diffusion constant were found to be 1.9 eV and 6.2×10-3 cm2/s, respectively. The electron carrier concentration profiles were also evaluated by spreading resistance profiling (SRP) to confirm dopant activation.

High-k Dielectrics for Ge, III-V and Graphene MOSFETs

It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Replacing SiO2 with high-k dielectrics in order to reduce gate tunneling currents has proven to be challenging, though it is now a manufacturable technique. Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility MOSFETs, using semiconductors from Column IV such as Ge and graphene, and III-V materials such as GaAs, InGaAs and InP. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics represents a marriage of necessity and convenience. It is known that atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through a self-limiting reaction. Furthermore, ALD can potentially offer the advantage of reducing native oxides by appropriate engineering of the precursor chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage from the beginning of ALD runs, while preventing the re-oxidation.

Evaluation of Electron and Hole Mobility at Identical Metal–Oxide–Semiconductor Interfaces by using Metal Source/Drain Ge-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

In contrast to high hole mobility of p-channel Ge metal–oxide–semiconductor field-effect transistors (MOSFETs), low electron mobility and poor current drive of n-channel Ge MOSFETs are one of critical issues for realizing Ge complementary metal–oxide–semiconductor (CMOS) technologies. In order to adequately understand the physical origins of the difference in the Ge MOS mobility behaviors between electrons and holes, an appropriate mobility analysis is strongly needed. In this paper, we propose a novel method to extract both electron and hole mobility in an identical device by using metal source/drain (S/D) Ge-on-insulator (GOI) MOSFETs. The influence of the parasitic resistance associated with metal S/D junctions is eliminated by using MOSFETs with four-terminal Kelvin patterns. It is demonstrated that the electron and hole mobility at the same Ge MOS interfaces are accurately determined. It is found, as a result, that the present Ge n-channel MOSFET has the electron mobility close to the Si universal electron mobility. On the other hand, the hole mobility at the same MOS interface is lower than the Si universal hole mobility, which is attributable to low crystal quality of the channel and/or the poor MOS interface properties. These facts strongly suggest the low electron mobility in Ge MOSFETs, reported so far, is not necessarily limited by any essential problems, but much higher electron mobility is expected by further improvement of the material and interface qualities.

Thermal SiO2 gated Ge metal-oxide-semiconductor capacitor on Si substrate formed by thin amorphous Ge oxidation and thermal annealing

The thermal SiO2 gated Ge metal-oxide-semiconductor (MOS) capacitor on Si substrate was accomplished by the direct oxidation of the amorphous Ge layer and a subsequent forming gas annealing. The epitaxial Ge on Si substrate shows the good crystallinity and the smooth interface with the thermal oxide. The oxide on the Ge layer is confirmed to have SiO2 bonding structure with tiny Ge content. The negligible hysteresis and the small frequency dispersion in C-V characteristics indicate the desirable oxide quality. The conduction mechanism through the oxide has been verified as Fowler–Nordheim tunneling with the conduction band offset of 2.81eV. Another intriguing point of this process lies in the fact that it provides a simpler and ultralarge scale integration-compatible approach to fabricate high-performance Ge MOS field effect transistors as compared with previous works.

Remote Phonon Scattering in Si and Ge with SiO2 and HfO2 Insulators: Does the Electron Mobility Determine Short Channel Performance?

We have computed the low-field electron mobility in inversion layers for single-gate metal–oxide–semiconductor-field-effect-transistor (MOSFET) structures with Si and Ge substrates and high-κ gate dielectrics. Scattering with bulk phonons, surface roughness, and surface optical phonons has been included. The mobility has been studied as a function of electron sheet density, gate dielectric, temperature, equivalent dielectric thickness and for polycrystalline Si and metallic gates. We have also performed full-band Monte Carlo simulations for Si and Ge MOSFETs with gate lengths of 60, 30, and 15 nm, employing SiO2 and HfO2 as gate dielectrics. Our results show that high-κ interface optical modes affect Si and Ge roughly by the same amount, the Ge mobility in HfO2 system still remaining larger than in the Si–SiO2 system. However, the low-field mobility does not entirely determine device performance, measured as transconductance. The transconductance degradation caused by high-κ phonons is much smaller than the mobility degradation, yielding a negligible negative impact, especially in Ge devices, shorter devices, and in the saturation region of operation.

Interface Properties of Room-Temperature-Grown Oxides on Si0.15Ge0.85 Layers

The electrical properties of room-temperature-grown oxides on Ge-rich SiGe layers are reported. X-ray photoelectron spectroscopy was used to investigate the room-temperature oxidation of thick Ge-rich layers on relaxed SiGe and Ge(001) substrates. The electrical properties of the oxides (as-grown and subsequently annealed) were studied using capacitance–voltage, conductance–voltage, and current–voltage characteristics of metal-oxide semiconductor (MOS) capacitors fabricated using these oxides. It is shown that the electrical properties of room-temperature-grown ultrathin oxides are reasonably good and may find applications in Ge MOS field effect transistors to improve the performance of future Ge complementary MOS technology. The effects of postmetal annealing on the interface state density and flatband voltage are also discussed.