Optimization of Germanium (Ge) $\hbox{n}^{+}/\hbox{p}$ and $\hbox{p}^{+}/\hbox{n}$ Junction Diodes and Sub 380 $^{\circ}\hbox{C}$ Ge CMOS Technology for Monolithic Three-Dimensional Integration

Abstract

In this paper, we optimize and investigate Ge n+/p and p+/n junction diodes formed by Co metal-induced dopant activation technique at the activation temperature range between 300 °C and 420 °C in terms of on/ off-current ratio. Combining this low-temperature n+/p and p+/n junction formation technique with a low-temperature gate stack comprised of Al/Al2O3/GeO2 by ozone oxidation technique, we demonstrate n- and p-channel Ge metal-oxide-semiconductor field-effect transistors (MOSFETs), respectively, at sub-360 °C and 380 °C. This low-temperature Ge MOSFET process can be utilized to integrate Ge complementary metal-oxide-semiconductor devices above interconnect layers for monolithic 3-D integrated circuits.