Ge Devices Research Articles

High performance 70 nm gate length germanium-on-insulator pMOSFET with high- k/metal gate

We demonstrate for the first time 70 nm gate length TiN/HfO 2 pMOSFETs on 200 mm GeOI wafers, with excellent performance: I ON = 260 μA/μm and I OFF = 500 nA/μm @ V d = −1.0 V (without germanide). These performance are obtained using adapted counterdoping and pocket implants. We report the best CV/ I vs. I OFF trade-off for Ge or GeOI devices: CV/ I = 4.4 ps, I OFF = 500 nA/μm @ V d = −1 V. Moreover, based on fine electrical characterizations ( μ, D it, R access, etc.) at T = 77–300 K, in-depth analysis of both ON and OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect I ON = 450 μA/μm, I OFF = 100 nA/μm @ V d = −1 V for L g = 70 nm.

Effects of Minority-Carrier Response Behavior on Ge MOS Capacitor Characteristics: Experimental Measurements and Theoretical Simulations

In this paper, we present MEDICI simulations of the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance Gsub and high-low transition frequency ftran, to explore the differences in the minority-carrier response. The Arrhenius-dependent Gsub characteristics revealed that a larger energy loss-by at least four orders of magnitude-occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of ftran. We confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency C- V curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al2O3/Ge MOS capacitors were consistent with the values of Gsub and ftran obtained from MEDICI predictions and theoretical calculations. In addition, upon increasing the inversion biases, we observed shifts in the Gsub/f conductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. ( 2-4) t1015 cm-3 exist in present-day low-doped Ge wafers.

High-Performance Gate-All-Around GeOI p-MOSFETs Fabricated by Rapid Melt Growth Using Plasma Nitridation and ALD $\hbox{Al}_{2}\hbox{O}_{3}$ Gate Dielectric and Self-Aligned NiGe Contacts

Rapid melt growth was used to fabricate gate-all-around germanium-on-insulator (GeOI) p-MOSFETs with plasma-nitrided Ge surface, Al2O3 high-k gate dielectric, and self-aligned NiGe contacts. The subthreshold swing is 71 mV/dec, which is better than those of the bulk and nanowire Ge p-MOSFETs reported to date. Planar GeOI p-MOSFET arrays show 40% hole mobility enhancement at a high effective field, which is as good as bulk Ge devices.

Effects of irradiation with gamma and beta rays on semiconductor Hall effect devices

The effects of short duration irradiation with low dose rate gamma and beta rays on the input resistance and the output Hall voltage of InSb, GaAs, Si, and Ge semiconductor Hall effect devices were systemically studied. Both gamma and beta irradiation can cause the input resistance of Hall effect devices to increase linearly with increasing irradiation time, in the absence of a magnetic field. When the devices were placed in a magnetic field, the output Hall voltage and input resistance increased nonlinearly with increasing gamma irradiation time. The effects of both gamma and beta irradiation persisted long after the irradiation itself, and without annealing. The effects from irradiation in Hall effect devices can be mainly ascribed to the degradation of the charge carriers’ transport properties caused by radiation-induced defects. The radiation resistance of the Hall effect devices was estimated by considering changes of the input resistance under the same irradiation conditions. The Ge and Si Hall effect devices demonstrated a better radiation resistance than the InSb and GaAs Hall effect devices due to their large displacement threshold energy.

Elimination of GeO 2 and Ge 3N 4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates

The contribution from relatively low -K SiON interfacial transition regions (ITRs) between Si and transition metal (TM) gate dielectrics places a significant limitation on equivalent oxide thickness (EOT) scaling for Si complementary metal-oxide-semiconductor (CMOS) devices. This limitation is equally significant and limiting for Ge CMOS devices. Low-K Ge-based ITRs in Ge devices have also been shown to limit performance and reliability, particular for n-MOS field effect transistors. This article identifies the source of significant electron trapping at interfaces between n-Ge or inverted p-Ge, and Ge oxide, nitride and oxynitride ITRs. This is shown to be an interfacial band alignment issue in which native Ge ITRs have conduction band offset energies smaller than those of TM dielectrics, and trap electrons for negative Ge substrate bias. This article also describes a novel remote plasma processing approach for effectively eliminating any significant native Ge ITRs and using a plasma-processing/annealing process sequence for bonding TM gate dielectrics directly to the Ge substrate surface.

Oxidation mechanism of hydrogen-terminated Ge(1 0 0) surface

Control of the surface chemistry to prepare a robust termination on the Ge surface is crucial for the development of high-end Ge devices. In this study, oxidation of a H-terminated Ge surface was studied in air ambient and H 2O using a multiple internal reflection Fourier transform infrared spectroscopy (MIR FT-IR) technique. Ge surface treated in less diluted HF exhibited a stronger Ge–H peak intensity, and the surface was easily oxidized in the air ambient. Therefore, it is believed that the treatment of the Ge surface in highly diluted HF solution has an advantage in suppressing the oxidation of Ge in the air ambient. For the oxidation of Ge(1 0 0) surface in air ambient, the Ge surface is attacked by oxidizing agents to break Ge–H and Ge–Ge bonds, and the transition GeO x layer is first formed, followed by a layer-by-layer GeO 2 formation with the increase in exposure time. When the H-terminated Ge surface was treated in H 2O, GeO x was mainly formed, the thickness of the oxide layer was not changed with an increase in treatment time, and the Ge surface was maintained in a suboxide state, which exhibits a different oxidation mechanism from that in air ambient.

Germanium metal-insulator-semiconductor capacitors with rare earth La 2O 3 gate dielectric

In this work, we investigate La 2O 3 as a gate dielectric candidate for Ge devices, using metal-insulator-semiconductor (MIS) structures. When the deposition temperature increases, the electrical characteristics improve with regard to dispersion in accumulation, hysteresis, stretch out, leakage current and interface state density D it. By analyzing the CV data for films with different oxide thickness we find that the dielectric constant of La 2O 3 has a medium k-value of about 11.The same data indicate that there is no interfacial layer, which is confirmed by high resolution transmission electron microscopy (HRTEM) observations. These results suggest that a strong reaction with the Ge substrate may take place so that a La-Ge-O compound may form over the entire film thickness reducing the k-value. This reaction layer could be responsible for the reduction of Dit indicating good passivating properties. However, it may limit gate oxide scaling in future Ge MOS devices.

Design and optimization of a buried channel PMOS integrable in a Si 1− xGe x BiCMOS process

A strained Si 1− x Ge x -channel PMOSFET, fully integrable in a standard Si 1− x Ge x BiCMOS process is proposed. It uses an n +-polysilicon emitter of the bipolar transistor as the gate, and has a p-type Si 1− x Ge x channel, making it a truly buried channel device. It uses only two extra masks and a few minor changes in the baseline BiCMOS flow, keeping the additional processing cost low. The basic device design is systematically optimized to get the best compromise among hole confinement in Si 1− x Ge x , layer stability and channel hole mobility. Optimization was done using Ge fraction dependent process and device simulation parameters for the first time. A novel, semi-analytical approach to model the effect of Ge fraction on hole current was used. The impacts of Si cap layer thickness, Si 1− x Ge x film thickness, channel doping and Ge fraction were investigated. During process and device design, care was taken to ensure that the Si 1− x Ge x layer remains strained as well as the standard available devices are not impacted by additional process steps. The optimized device shows a 2× gain in transconductance and in drain current over the standard PMOS device available in the baseline process.

Remote Phonon Scattering in Si and Ge with SiO2 and HfO2 Insulators: Does the Electron Mobility Determine Short Channel Performance?

We have computed the low-field electron mobility in inversion layers for single-gate metal–oxide–semiconductor-field-effect-transistor (MOSFET) structures with Si and Ge substrates and high-κ gate dielectrics. Scattering with bulk phonons, surface roughness, and surface optical phonons has been included. The mobility has been studied as a function of electron sheet density, gate dielectric, temperature, equivalent dielectric thickness and for polycrystalline Si and metallic gates. We have also performed full-band Monte Carlo simulations for Si and Ge MOSFETs with gate lengths of 60, 30, and 15 nm, employing SiO2 and HfO2 as gate dielectrics. Our results show that high-κ interface optical modes affect Si and Ge roughly by the same amount, the Ge mobility in HfO2 system still remaining larger than in the Si–SiO2 system. However, the low-field mobility does not entirely determine device performance, measured as transconductance. The transconductance degradation caused by high-κ phonons is much smaller than the mobility degradation, yielding a negligible negative impact, especially in Ge devices, shorter devices, and in the saturation region of operation.

High performance, waveguide integrated Ge photodetectors

Photonic systems based on complementary metal oxide semiconductor (CMOS) technology require the integration of passive and active photonic devices. The integration of waveguides and photodetector is one of the most important technologies. We report a Ge p-i-n photodetector that is monolithically integrated with silicon oxynitride and silicon nitride waveguides. All processes and materials are CMOS compatible and can be implemented in the current integrated circuit process technology. The small size of the devices results in low absolute dark current. The waveguidecoupled Ge devices show high efficiency (~90%) over a wide range of wavelengths well beyond the direct band gap of Ge, resulting in a responsivity of 1.08 A/W for 1550 nm light. The device speed of 7.2 GHz at 1V reverse bias is strongly affected by the capacitance of the probe pads. The high-performance of the devices at low voltage ( </= 1V) facilitates the integration with CMOS circuits.

Infrared emission from Ge metal-insulator-semiconductor tunneling diodes

The Ge light-emitting diode with ∼1.8μm strong infrared emission is demonstrated using a metal-insulator-semiconductor tunneling structure. The intensity of a Ge device is one order of magnitude stronger than a similar Si device. At the positive gate bias, the holes in the Al gate electrode tunnel to the n-type Ge through the ultrathin oxide and recombine radiatively with electrons. An electron-hole-plasma model can be used to fit all the emission spectra from room temperature down to 65K. From the measurement temperature range, the extracted band gap is ∼40meV lower than the reported band gap data, and the linewidth drops from 70to25meV. The longitudinal acoustic phonon (∼28meV) and/or the band gap renormalization at high carrier density are proposed to be responsible for the reduction of photon energy. The band gap reduction on the mechanically strained n-type Ge and Si is also investigated experimentally and theoretically.

Germanium MOS technology for infra-red detectors

Fabrication of an electrically stable dielectric is a key enabling technology in the production of a Ge detector with enhanced response in the near infra-red spectrum. This work investigates the physical and electrical properties of silicon dioxide (SiO 2) dielectrics deposited on Ge substrates. The deposited SiO 2 (silox) layers have been densified at 600 and 800 °C. Significant Ge outdiffusion from the substrate into the densifying silox layer has been observed for the 800 °C process, and the diffusivity has been estimated as 1.5×10 −4 μm 2/min. The C– V characteristics of Ge MOS capacitors incorporating this silox dielectric display the onset of ‘low frequency’ operation at a relatively high frequency of 100 kHz, and the capacitor C– t response suggests that Ge carrier lifetime is much shorter than that measured for Si MOS capacitors. These phenomena are shown to result from the narrow band gap of Ge, and this work therefore emphasises that increased cooling will be required to exploit the infra-red detector properties of a practical Ge device.

Electron Transport in Engineered Substrates: Strain, Orientation, and Channel/Insulator Material Effects

We present theoretical results regarding electronic transport in different types of `unconventional' substrates and structures: (a) In uniaxially and biaxially strained Si for a variety of substrate, transport-direction and strain orientations, showing that compressive strain on (110) surfaces may enhance simultaneously the electron and hole mobility; (b) In short-channel Si, Ge, and InGaAs bulk and double-gate FETs, showing that at the 15 nm length the `density-of-states' bottleneck reduces drastically the performance of small-mass materials. We also discuss the role of Zener leakage in these small devices, process which is particularly severe in Ge devices; (c) In Si and Ge high-k systems, showing that electron mobility in Ge inversion layers is also seriously affected by high-k phonons, but that the loss of performance -- measured in terms of transconductance -- vanishes at short channel length for both Si and Ge devices.

Nickel Selective Etching Studies for Self-Aligned Silicide Process in Ge and SiGe-Based Devices

The limitations of the H2SO4/H2O2/H2O mixture (diluted SPM chemistry) as a reagent for the nickel selective etching step of the salicidation process when silicon is replaced by silicon- germanium alloys or pure germanium is investigated. When the Ge content in SiGe is higher than 30%, SPM is not suitable anymore due to the high etch rate of the germanosilicide layer. This high etch rate is related to the poor stability of the Ge oxide in aqueous solutions. For Ge contents above 30%, H2SO4 96% is proposed as a selective etching reagent instead of SPM. With this chemistry, a very high Ni/NiSiGe selectivity and a good Ni/NiGe selectivity are obtained, since only 10% of the germanide layer is attacked while the Ni layer is completely removed.

Thin epitaxial Si films as a passivation method for Ge(1 0 0): Influence of deposition temperature on Ge surface segregation and the high-k/Ge interface quality

Epitaxial fully strained Si films are known to form an effective passivation of the Ge(1 0 0) surface. However, we show using low-energy secondary ion mass spectrometry (SIMS) that considerable Ge surface segregation occurs for Si films grown from SiH 4 at 500 °C. In this study, we develop an alternative deposition process at 350 °C using Si 3H 8 which significantly decreases the Ge peak at the Si surface. We attribute this strong reduction mainly to the fact that growth at 350 °C from trisilane proceeds below the Si–H desorption temperature. Charge pumping measurements on n-type Ge devices show a reduction by approximately a factor three in the high-k/substrate interface trap density for the samples with 350 °C Si passivation, compared to those using a Si passivation deposited at 500 °C.

Thermochemical reaction of ZrOx(Ny) interfaces on Ge and Si substrates

We have studied the thermochemical characteristics of ZrOx(Ny)∕Ge and Si interfaces by employing postdeposition annealing. We found that Ge oxide species severely desorbed from the inherent interfacial layer, which was speculated to retard the formation of Zr germanate during high-temperature processing. These unique features enable ZrOx(Ny)∕Ge gate stack to show a better equivalent-oxide-thickness scalability as compared to ZrOx(Ny)∕Si gate stack. However, the volatilization of GeOx-contained interfacial layer also caused the formation of small pits and/or holes in the overlying ZrOx(Ny) gate dielectrics, which was expected to cause deterioration in the electrical properties of fabricated high-k∕Ge devices.

Modeling of non-equilibrium transport effects in Fully-Depleted GeOI-MOSFETs

Germanium is investigated as basic semiconductor for advanced CMOS nodes. A mobility model at low fields for Ge devices is developed starting from the CVT model, whose parameters are calibrated by comparison with experiments. TCAD simulations of Fully-Depleted (FD) Germanium-On-Insulator (GeOI) n- and p-MOSFETs are presented using both the drift-diffusion and the energy balance transport models. Effects due to non-equilibrium transport in small devices are estimated by varying the energy-relaxation time of the Ge material and by analyzing the phenomenon of velocity overshoot in the channel. It is found that GeOI MOSFETs furnish robust performance improvements when short device lengths are considered due to the influence of non-local effects.

Monte Carlo study of strained GermaniumNanoscale bulk pMOSFETs

In this paper, we perform fullband Monte Carlo simulations of nanoscale strained Ge bulk pMOSFETs with compressive strain in the strained Ge layer. We consider transport in the presence of phonon, ionized impurity, surface roughness scattering and impact ionization. Quantum confinement in the inversion layer is taken into account in the form of a modified potential. Strained Gedevices gave higher drive current when compared with unstrained Ge devices for the device structures studied.

Thermal Stability of a Reverse-Graded SiGe Buffer Layer for Growth of Relaxed SiGe Epitaxy

We have recently developed a novel reverse-graded (RG) buffer system, in which the Ge content decreases with distance from the Si interface. These thin (90 nm) RG layers are capable of supporting the growth of relaxed SiGe layers (85% relaxed) with defect densities as low as 10 5 /cm 2 . Good quality strained Si has also been successfully grown on these substrates. However, the thermal stability of this novel heterostructure has not been explored. In this paper, we establish, by high-resolution X-ray diffraction, Raman spectroscopy, atomic force microscopy, and transmission electron microscopy, that the heterostructure is stable up to 1000°C with no further strain relaxation in both the RG layer and strained Si layer. Hence, it is clear that this thin RG heterostructure is highly suitable as a buffer system for the growth of high-mobility strained Si or Ge devices.

Prospects and challenges of Ge device technology

Prospects and challenges of Ge device technology