Ge Condensation Technique Research Articles

Stress Relaxation of Extremely-Thin-Body Ge-on-Insulator p-Type Metal-Oxide-Semiconductor Field-Effect Transistor Along and Observed By Oil-Immersion Raman Spectroscopy

Background and purpose Strain techniques and channel materials with high carrier mobility are the principal technology boosters for the realization of high-performance logic devices composed of group IV semiconductors such as silicon (Si). In particular, strain engineering plays an important role in improving the performance of metal-oxide semiconductor field-effect transistors (MOSFETs) from the viewpoint of reducing the effective carrier mass. It is important to evaluate the stress relaxation in group IV semiconductor devices for the optimization of the carrier mobility and the device structure. In this paper, we demonstrated the stress evaluation of extremely-thin-body Ge-on-insulator (ETB GOI) p-type MOSFET along the <110> and <100> longitudinal directions by oil-immersion Raman spectroscopy with the high-numerical-aperture (high-NA) lens to realize precise evaluation of strain states in the Ge channels. Experiments Biaxially-strained (001) GOI layer was prepared by applying optimized Ge condensation technique on epitaxially-grown Si/Si0.75Ge0.25/Si-on-insulator substrates with 4-hour slow cooling [1, 2]. After the removal of the thermal oxide, narrow channel patterning was performed by electron-beam (EB) lithography. GOI channel was further thinned down by the cyclic digital etching process (plasma oxidation and wet etching). Surface passivation process was then immediately performed to fabricate GeO x and Al2O3 by plasma oxidation and atomic layer deposition at 300oC, respectively. The source-drain regions were formed with EB evaporated Ni through a lift-off process and Al deposition was performed as the back gate electrode.We used the Raman spectrometer with spectrograph focal length of 2,000 mm. The numbers of grating grooves were 2,400 mm-1 and a visible laser was used as the incident excitation light source whose wavelength was 532 nm. To realize anisotropic stress evaluation assuming the channel region of the ETB GOI MOSFET, we used a high-NA immersion lens for the selective excitation of both LO and TO phonon modes [3]. The high-NA and refractive index n of the oil were approximately 1.4 and 1.5, respectively. Using a high-NA immersion lens, a z-polarized light component can be effectively obtained owing to the aperture angle. Therefore, TO phonons can be excited on the basis of Raman selection rules for (001)-oriented GOI [3, 4]. Results and discussion Figure 1 shows the channel width dependence of the anisotropic biaxial stress of ETB GOI MOSFET along the <100> longitudinal direction obtained by the oil-immersion Raman spectra. Anisotropic biaxial compressive stress at the GOI channel width direction of the GOI channels was observed even when the GOI channel width is wide (GOI channel width ~ 630 nm). The stress along the GOI channel length (the <100> longitudinal direction) is relatively high. These results are clearly different from the stress relaxation in the ETB GOI MOSFET along the <110> longitudinal direction. In previous studies, a clear stress relaxation at the GOI channel width direction was observed as the GOI channel width becomes narrower of the ETB GOI MOSFET along the <110> longitudinal direction (from channel width ~ 200 nm) [5]. The results observed in this study are generally well correlated with the results obtained in strain relaxation measurements of carbon-doped Si nanowires along <100> by X-ray diffraction with synchrotron radiation [6]. The difference in the strain relaxation mechanism depending on the GOI channel direction may affect the electrical properties, and we consider that it is useful to be physical elucidation of the carrier mobility enhancement. Acknowledgements This work was supported by JSPS KAKENHI Grant Number 22H00208, Japan. A part of this work was con-ducted at Takeda Sentanchi Supercleanroom, The University of Tokyo, supported by "Nanotechnology Platform Program" of MEXT, Japan, Grant Number JPMXP09F-20-UT-0007.

(Invited) Layer Transfer Technology for Stacked Multi-Channel Semiconductor-on-Insulator Platform

Continuous scaling of device dimension pushed Si channel to its physical limit, alternative high mobility channels such as (Si)Ge and (In)GaAs have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power dissipation CMOS. To realize stacked multi- channel semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology [1-3] utilizing direct bonding and selective etching was developed to integrate (Si)Ge or (In)GaAs channels on Si, showing great potential for ultimate device structures with heterogeneous integration.Figure 1(a) is the process flow for integrating InGaAs channel onto SiGe-on-insulator (SGOI) structure utilizing layer transfer technology [4]. It started with bottom SGOI pMOSFET fabrication. The SGOI structure was realized by 2-step Ge condensation technique, resulting in Ge content of 70%. After high k metal gate process, self-aligned Ni-SiGe alloy was formed as S/D metal. Subsequently, SiO2 interlayer was deposited by CVD, followed by CMP planarization. Then, InGaAs grown on InP was directly bonded onto SiO2 and InP substrates were selectively etched away. Finally, the top InGaAsOI nMOSFET fabrication and metal interconnection completed the CMOS fabrication. Fig. 1(b) shows the cross-sectional TEM images of fabricated InGaAs/SiGe channel stacked CMOS. Well aligned top and bottom devices are seen without any distinct defects.Figures 2 is a schematic flow for fabricating Ge/Si double channel-on-insulator structure by low temperature hetero-layer bonding technology (LT-HBT). The technology starts with the preparation of donor wafers (Fig. 2(a)) for the top Ge channel layer and host wafers (Fig. 2(b)) for the bottom Si channel layer. For donor wafers, a 200-nm-thick Ge was epitaxially grown on SOI wafer by reduced pressure CVD. After CMP planarization, ALD SiO2 is deposited onto Ge. For host wafers, implantation and dopant activation were carried out, followed by chemical treatment for Si oxidation. After surface activation by room temperature chemical treatment (Fig. 2(c)), the direct wafer bonding of both SiO2 surface was performed at 200 °C in a press machine (Fig. 2(d)). Then, the Si substrate of the donor wafer was removed with deep RIE. At this time, the BOX layer of the donor wafer serves as an etch-stop layer. Subsequently, the BOX layer and thin Si layer of the donor wafer were removed selectively in HF and TMAH solution, respectively (Fig. 2(f)). To precise control the top Ge channel thickness, a series of low damage etching process was adapted to thin down Ge (Fig. 2(g)). The realized double channel structure is fully isolated with an insulating insertion layer,[5] which is very promising for realizing novel complementary FET (CFET) with minimum process steps. The cross-sectional TEM image of Ge/Si stacked channel of CFET after high k metal gate process is demonstrated in Fig. 2(h). Even more multiple stacks can be realized by using LT-HBT. A vertically stacked three-layer structure with 2 bottom Si layers and 1 top Ge layers is also demonstrated using SOI-based donor wafers in Fig. 3, indicating the highly integrated density channel structure is possible. The feasibility of layer transfer technology has been proved for multi-channel structure with high mobility channels for N2 node and beyond. Acknowledgement This work was supported by JST Japan-Taiwan Collaborative Research Program, Grant Number JPMJKB1902, Japan and the Ministry of Science and Technology under Grant Number MOST-109-2628-E-492-001-MY3, 109-2923-E-492-001-MY3, 107-2221-E-492-016-MY3.

Vertically-Stacked Si0.2Ge0.8 Nanosheet Tunnel FET With 70 mV/Dec Average Subthreshold Swing

A novel CMOS-compatible SiGe Tunnel Field-Effect Transistor (TFET) with a high current drivability is demonstrated, which features a vertically-stacked SiGe nanosheet (NS) with high Ge content and gate-all-around(GAA) structure to improve carrier injection efficiency and gate controllability. A multi-NS Si 0.2 Ge0.8 channel is formed by the Si selective etching and Ge condensation technique. The measured data shows both the 50 mV/dec minimum subthreshold swing (SS) and 70 mV/dec average SS over 3 decades of drain current change. Compared to previously reported devices, it is clear that the proposed SiGe nanosheet TFET can achieve steeper switching and low-level leakage current with a low drive voltage as an alternative to conventional MOSFET.

Fabrication of SiGe/Ge nanostructures by three-dimensional Ge condensation of sputtered SiGe on SiO2/Si substrate

In this work, three-dimensional (3D) Ge condensation of sputtered “Si/SiGe” nanostructures on SiO2/Si substrate was investigated. Through varying the width of sputtered Si/SiGe structures from 50 μm to 400 nm, the Ge content of fabricated SiGe structures can be modulated from 0.49 to 1.0 after 3D Ge condensation. By further constructing a width modified nanowire (NW) with adjacent widths of 800 nm and 400 nm before 3D Ge condensation, a Si0.33Ge0.67/Ge heterostructure NW was fabricated after 3D Ge condensation. Due to inter-diffusion of Si and Ge atoms, a ∼2-μm-long region with gradually varied Ge content from ∼0.67 to 1.0 is formed between Si0.33Ge0.67 and Ge. The low Schottky barrier height (0.29 eV) of Ge NW/metal contact and good conductivity of the Ge NW suggest that the 3D Ge condensation technique is very promising for fabrication of scalable and low-cost SiGe or Ge nano-electronic/photonic devices.

Broadband 400-2400 nm Ge heterostructure nanowire photodetector fabricated by three-dimensional Ge condensation technique.

A 2.7% tensile strained Ge/SiGe heterostructure nanowire (NW) is in-situ fabricated by a three-dimensional Ge condensation method. The NW metal-semiconductor-metal (MSM) photodetector demonstrates an ultra-broadband detection wavelength of 400-2400 nm, showing a high responsivity of >3.46×102 A/W with a photocurrent gain of >4.32×102 at 1550 nm under -2 V. A high normalized photocurrent to dark current ratio (NPDR) of 1.88×1011 W-1 at 1550 nm under -1 V is achieved. The fully complementary metal-oxide-semiconductor (CMOS) compatible, simple and scalable process suggest that the Ge heterostructure NW is promising for low cost, high performance near-infrared or short wavelength infrared focal plane array applications.

Strain evolution of SiGe-on-insulator obtained by the Ge-condensation technique

Compressively strained SiGe-On-Insulator (SGOI) made by the Ge-condensation technique is used as a performance booster for ultrathin fully depleted silicon-on-insulator transistor technology. Here, we report on the evolution of the compressive strain in the SiGe film along the formation of local SGOI. For this, experimental maps of lattice strain with nanometer spatial resolution have been obtained by dark-field electron holography and compared to results from numerical models describing the mechanics of the structures. In particular, we report on unexpected strain evolutions when the top semiconductor layer is patterned to fabricate the shallow trench isolations that separate the Si nMOS from the SiGe pMOS areas. Dramatic and long-range relaxation of the compressive SiGe layers occurs, while no extended defects are formed in the crystal. The phenomenon involves relative horizontal displacements between the SiGe layer and the underlying Buried Oxide (BOX). We suggest that the Ge-enrichment of the layer close to this interface by the Ge-condensation technique modifies the SiGe/BOX interface and that strain relaxation results from the propagation of some interfacial defects from the edge to the center of the structure, driven by the shear stress at the interface.

(Invited) Impact of Some Processing Steps onto the Strain Distributions in FD-SOI CMOS Planar Devices: A Contribution of Dark-Field Electron Holography

For long time considered as detrimental, stress is now an integral feature of modern electronic devices. Indeed, correctly oriented, the resulting strains may significantly increase carrier mobility and thus boost device performance. In this context, Dark-Field Electron Holography (DFEH) was used to study the impact of some key steps of the manufacturing process of 22 nm fully depleted planar transistors (FDSOI). DFEH is an interferometry technique based on Transmission Electron Microscopy recently invented and still being developed at CEMES-CNRS, which allows us to map crystalline strains with nanometer resolution and an accuracy of 10-4 over micrometer fields of view. The comparison of these experimental maps with simulation results obtained from Finite Element Modelling (FEM) allows one to explore, then possibly identify, the mechanical phenomena involved during the processing steps of FDSOI transistors. In general, samples are fabricated using a Focused Ion Beam equipment and thinned down to 80-110 nm. Thus they suffer some elastic relaxation at, and close to, the two free surfaces. FEM is used to reproduce the observed strain in the same thin “measured sample”, taking into account the influence of thickness on the electron wave amplitudes and resulting phase contributions to the final hologram, then to retrieve the strain which was originally present in the bulk sample. Based on our (long) experience, these physically sound refinements never alter the measurements by more than 15%, most often by a mere 5%, for the planar devices we observe. In other words, the mappings directly obtained by DFEH reproduce very well the actual strain fields which reside in the transistor before thinning. Following the different steps leading to the co-integration of n and p-MOS, from the “Ge condensation technique” to locally form a thin highly compressively strained SiGe layer to the opening of trenches, we have evidenced abnormal large strain relaxations of these layers at the trench edges, extending well beyond elasticity predictions. Numerical approaches suggest some “weakened interface” exist between the SiGe layer and the BOX. It can be simulated introducing weak elastic spring forces to bind the interface, instead of the foreseen rigid connection. Later confirmed by Raman and electrical studies and despite various hypothesis have been investigated (H, Ge-O bonds…), this phenomenon remains unexplained. The figure shown above is a composite image of the strain along the channel of the foreseen n-MOS after the fabrication of the gate stack on the Si thin top layer. The stack was deposited “full sheet” and involves several different materials and energetic thermal treatments (oxidation, ALD, CVD, activation annealing, etc). In full sheet, the internal stresses cannot relax. Then, when the gates are fabricated by photolithography and etching, the symmetry breaking (edges) allows the various layers to react to these internal stresses and deform. This image shows that the channel is under tension (in plane) below the gate, with a maximum strain of about 0.8%. The gate tends to relax some internal compressive stress and deforms the underlying, originally unstrained Si channel. The same phenomenon is observed on the SiGe layers for p-MOS transistors, which are under compression after their fabrication by the Ge enrichment technique. The stress exerted by the gate is mostly due to presence of the TiN contact which, when back at room temperature after deposition, is highly compressively stressed (-2.35 GPa). This contact transfers its deformation through the gate dielectric putting the channel under tension. This effect is consolidated by the opposite effect of the SiN spacer (intrinsically tensile) which tends to compress further the Si film on both sides of the channel. Finally, we will follow two subsequent and important processing steps; the fabrication of the raised source and drain and of the contact silicide. Both steps affect the strain state of the channel of the devices (n- and p-MOS). The composition of the source and drain (Si, Ge, B, P, C…) can be craftily adjusted to manipulate further strain in the channel of the devices. Silicidation of the source and drain has almost no effect on the strain state of the channel as the raised source and drain can relax laterally without affecting the channel. Partial BOX creeping at high temperature and strain relaxation at free edges are the main ingredients needed to understand and simulate the strain behavior of the channel during these fabrication steps. In most cases, DFEH images not only provide more precise results than Nano Beam Diffraction (NBD) but additional important information such as the presence of defects, precipitates, heterogeneous compositions, etc., all locally but strongly impacting strain distributions. Figure 1

High sensitivity biosensors based on germanium nanowires fabricated by Ge condensation technique

We demonstrate a novel technique to fabricate germanium nanowires (GeNWs) for field effect transistor biosensors. Arrays of core-shell structure GeNWs were “top-down” fabricated by combining the complementary metal-oxide semiconductor (CMOS) compatible technology and Ge condensation technology. The obtained GeNWs had stable SiO2 cladding, which acted as good modification platform for biochemical detection, since SiO2 modification was a mature technology. After the GeNWs were covalently bonded with DNA probe, the nanosensor demonstrated highly sensitive concentration-dependent current change in response to target DNA. This study may pave the way for further application such as the integration of bioelectronics and biosensors with the attractive semiconductor material Ge in future work.

Ge-on-insulator wafer with ultralow defect density fabricated by direct condensation of SiGe-on-insulator structure

This letter presents an improved method to fabricate Ge-on-insulator (GOI) wafer with extremely low defect density. In the traditional Ge condensation approach, the Si/SiGe/SOI structure is utilized as the starting substrate, and the misfit dislocations formed at the SiGe/SOI interface will evolve into the threading dislocations during the Ge condensation process, thus resulting in high density of defects residual in the final GOI wafer. In the present study, the defect evolution process is precluded via the direct condensation of SiGe-on-insulator (SGOI), which is fabricated by ion-cut technique prior to the Ge condensation. Compared to the traditional Ge condensation approach, the threading dislocation density (TDD) of GOI obtained by the improved method is significantly reduced from 1×107cm−2 to 7×105cm−2. In addition, a considerable enhancement (56%) of the hole mobility for the modified Ge condensation approach is achieved. Our modification may bring the revival of the Ge condensation technique in GOI wafer manufacturing and enable the potential application in post-silicon era.

Strain/composition interplay in thin SiGe layers on insulator processed by Ge condensation

We study the interplay between strain and composition during the elementary process steps which allow the fabrication of strained ultra-thin SiGe layers on insulators from a Silicon-On-Insulator (SOI) substrate by the Ge condensation technique. Strain maps with subnanometer resolution and high precision are obtained using the dark-field electron holography technique. We confirm that two basic mechanisms drive the final composition of the top layer, namely Ge injection during oxidation and Si/Ge interdiffusion, both thermally activated. We show that during this process the observed strain results from the out-of-plane relaxation of the stress generated by the substitution of Si by Ge atoms in the Si lattice, rigidly bounded to the underlying buried oxide.

Sb-Doped S/D Ultrathin Body Ge-On Insulator nMOSFET Fabricated by Improved Ge Condensation Process

We report the demonstration of ultrathin Ge-on-insulator (GOI) inversion-type nMOSFETs, fabricated by the optimized Ge condensation technique and solid-phase diffusion of Sb. The GOI structures with low hole concentration of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> or less are realized by optimizing oxidation temperature and inserting annealing process for enhancement of intermixing in the Ge condensation process recipe. The hole concentration in the GOI body has been systematically analyzed with different oxidation temperature and insertion of annealing process. Highly doped n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> source/drain regions are formed in 16-nm-thick GOI layers by Sb solid-phase diffusion doping from spin-on-glass at 650°C. The high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /IO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FF</sub> ratio of 104 is observed in the fabricated nMOSFETs. The peak electron mobility of 107 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs is obtained for the inversion-type GOI nMOSFETs.

(Invited) Mobility Enhancement of Uniaxially Strained Germanium Nanowire MOSFETs

Strained Ge nanowire MOSFETs with a compressive strain as high as -3.9 % were fabricated by the 2-step Ge-condensation technique without intentional doping for the S/D. Record high hole mobility (μ eff = 1992 cm2/Vs @ N s = 1.7x1012 cm-2) was achieved among Ge nanowire pMOSFET ever reported. Inserting a plasma-oxide (GeOx) inter-layer between the high-k dielectric and the strained Ge nanowire channel greatly improved not only the mobility but the cut-off characteristics. A low off-current (2.7 nA/μm at V d = -0.5 V) was achieved by the device with the gate length of 45 nm, thanks to the reduced interface state density.

(Invited) Mobility Enhancement of Uniaxially Strained Germanium Nanowire MOSFETs

Introduction High mobility channel materials are extensively explored to replace strained-Si in MOSFET devices to reduce power consumption by lowering supply voltages, V dd, without degrading circuit performance. Among the various high mobility channel materials, compressively strained-Ge[1-4] is recognized as the most promising option for p-channel FETs due to its significantly high hole-mobility and compatibility with Si-CMOS process. In this paper, Ge nanowire MOSFETs with a uniaxial compressive strain as high as 3.9% were demonstrated by 2-step Ge-condensation technique. Record-high hole mobility (μ eff = 1922 cm2/Vs) and record-low off-current (2.7x10-9A/μm at V d = -0.5V) were achieved among scaled (sub-100nm L g) Ge MOSFET for the device with the L gof 45nm. Device fabrication Uniaxially strained-Ge nanowire channel was formed by the two-step Ge condensation technique, which induced uniaxial stress along the channel direction[3]. As a gate insulator, 5 nm thick Al2O3 was grown by using ALD. Partly, in order to improve the interface characteristics and hole mobility, MMT-plasma oxidized GeOx / 3.2 nm-Al2O3 stacked gate insulator were adopted[4,5]. Ni(Si)Ge-metal S/D structures were formed by SALICIDE-like process. Detailed device fabrication process was shown in [4]. The Relationship between the wire width, W wire and strain applied to the channel was measured by an immersion high-NA Raman spectroscopy[6] and a NBD measurement. The dependence of strain along the channel direction, ε xx on wire width is shown in Fig.1. Extremely high (-3.8%) strain was evaluated for W wire= 20 nm device, which was almost identical with the value obtained from the NBD measurement. Moreover, extremely high (over -3.9%) strain, which is almost identical with the misfit strain between Ge and Si, was evaluated by strained-Ge nanowire channel formed by improved two-step Ge condensation technique[4]. Mobility enhancement by uniaxial compressive strain In order to estimate the mobility enhancement factors in uniaxially strained-Ge and Si1-x Ge x inversion channels, Poisson-Schrodinger self-consistent solver[7] was used to calculate the effective mass (m eff) values. Here, 6x6 k*p method was used. Figure 2 shows the calculated Ge concentration dependence of inversion layer effective hole mass along [110] channel direction. For Ge (x=1), m eff was calculated to be 0.055m 0 at fully strained condition, i.e., the lattice constant is identical with that of Si in [110] directions. Considering the ratio of m eff, 12 times higher mobility that for unstrained Si can be expected on uniaxially strained-Ge. At these highly strained condition, orientation dependence among (001), (112) and (110) is diminished due to the band deformation. Device characterization Hole mobility was extracted by a split CV method for long-channel and multi-wire devices. Figure 3(a) shows hole-mobility of the fabricated multi-wire MOSFETs. The W wire = 40nm device, which has 95% Ge channel and GeOx / Al2O3 stacked gate insulator, showed a peak hole mobility of 1922 cm2/Vs at N s = 1.7x1012cm-2, which exceeds that of -3.8% strained-Ge nanowire MOSFET with Al2O3 gate stack. Moreover, the obtained mobility at N s = 5x1012cm-2 is corresponding to 5.8 times of the counterpart of a state-of-the-art strained-Si pMOSFETs[1]. Figure 3(b) shows that mobility values for fixed N s increased with Ge concentration, x. The tendency is consistent with the m eff calculation in Fig.2. Figure 4 shows I d-V g characteristics of fabricated strained-Ge nanowire pMOSFET with GeOx / Al2O3 stacked gate insulator. Ion/Ioff ~ 105 has also been attained. And a minimum drain leakage current (I d,off), as low as current 2.7x10-9A/μm at V d = -0.5V, were achieved with L g = 45 nm. This I d,off value is the lowest minimum drain leakage among the previously reported sub-100nm L g strained-Ge devices even though that has a shortest L g. Conclusion s Ge nanowire MOSFETs with a uniaxial compressive strain as high as 3.9% were demonstrated by 2-step Ge-condensation technique. Record high hole mobility (μ eff = 1922 cm2/Vs) and record-low off-current (2.7x10-9A/μm at V d = -0.5V) were achieved among scaled (sub-100nm L g) Ge MOSFET for the device with the L gof 45nm. These results indicate that strained-Ge channels have a potential to serve as pFET channel of scaled future CMOS.

Ge Condensation Using Rapid Thermal Oxidation for SGOI Substrate Preparation

High mobility channels are considered as an interesting path to increase PMOS performances for advanced CMOS technology. Silicon-Germanium On Insulator (SGOI) benefits from both the advantage of the SiGe material (hole mobility booster) and the On Insulator structure (better electrostatic control of the channel by the gate) [1]. The co-integration of NMOS and PMOS, respectively on Silicon On Insulator (SOI) and SGOI zones, can be enabled easily by the Ge condensation technique [1,2]. This technique is based on the competition between Ge diffusion and Si oxidation which are both driven by temperature. For this purpose, mainly furnace oxidation is reported in the literature [1-3]. In this work, we propose to study Ge condensation using Rapid Thermal Oxidation (RTO) as an alternative process.SGOI structures were fabricated on 300mm SOI wafers, with 11nm thick top silicon. First, epitaxy layers of SiGe were grown with varying thickness (from 3 to 10nm) and Ge concentration (from 10 to 40%). The SiGe film was grown by Rapid Thermal Chemical Vapor Deposition at temperature between 600°C and 650°C. Then, Ge condensation was performed by RTO in O2 ambient at temperatures between 950°C and 1150°C. Both aspects of Ge condensation were studied: Ge diffusion then Si oxidation.The RTO temperature effect on Ge diffusion was analysed by ToF-SIMS (Figure 1). In the case of short oxidation duration (below 2 minutes), as typically used in RTO compared to furnace (several hours), almost no diffusion is observed at 950°C. This leads to Ge enrichment of the initial SiGe layer with Ge concentration gradient. For longer oxidation, this might result in very high Ge concentration generating strain relaxation via stacking fault creation [4]. Therefore, temperatures above 950°C are prefered to avoid defects creation. TEM and STEM-EDX of the structure after condensation (Figure 2) shows that Ge concentration is still not totally homogeneous at 1100°C.Oxidation kinetics is shown on Figure 3, comparing the effect of substrate: SiGe/Si/BOX vs Si. SiGe is oxidized faster than Si, as already reported [5,6]. Moreover, SiGe oxidation is enhanced with increasing Ge concentration. Same trend is observed concerning SiGe thickness, indicating the effect of Ge diffusion in the underneath Si layer.A compositional analysis of the oxide grown by condensation was performed by XPS, monitoring the Ge3d peak (Figure 4). Starting from the same SiGe/Si/BOX structure, the oxide thickness was kept the same using different RTO temperatures but tuning the O2 pressure and the RTO duration. The effect of Ge diffusion is clearly observed by the intensity of the Ge-Si contribution. Higher temperature leads to lower Ge concentration due to a more homogeneous Ge distribution. Surprisingly, Ge-O bounds are also observed, whereas SixGe1-xalloy oxidation is thermodynamically considered to be Si selective [7]. Moreover, the amount of Ge-O bounds increases when the RTO temperature decreases. As shown previously, low temperature oxidation leads to high Ge concentration at the SiO2/SiGe interface, which may enable the formation of Ge-O bounds [8]. As a consequence, oxidation kinetics plays an important role in this phenomenon.This study reveals the significant role of temperature in Ge condensation by RTO. Due to kinetics effect, Ge-O bounds are formed which is not predicted by thermodynamics. Finally, the role of temperature will be investigated through electrical characterization of the SixGeyO properties.[1] B. Vincent at al, Mat. Sc. Semicond. Proc. 11, 2008[2] T. Tezuka et al., Jpn. J. Appl. Phys. 40, 2886, 2001.[3] Z. Di et al., J. Crystal Growth 281, 2005[4] B. Vincent, Appl. Phys. Lett. 90, 2007[5] O. W. Holland et al., Appl. Phys. Lett. 51, 7, 1987[6] S. J. Kilpatrick et al., J. Appl. Phys. 81, 12, 1997[7] D. C. Paine et al, J. Appl. Phys. 70, 5076, 1991[8] J. Eugene, Appl. Phys. Lett. 59, 78, 1991

(Invited) Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node

Performance enhancement using conventional stress elements such as stress liners or embedded source/drain is significantly decreased at extremely tight gate pitch, required for 10nm node and beyond [1]. This issue is more pronounced for non-planar architectures such as FinFETs, especially those made on SOI substrates. For p-type MOSFETs, SiGe is a great candidate due to its intrinsic lower effective mass and better transport properties than Si. SiGe has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a knob to adjust the PFET threshold voltage and performance enhancement [2, 3]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable short-channel benefit over Si and as a result, strain plays a significant role in high-performance SiGe channel pFETs [4]. While higher Ge content SiGe materials can offer lower effective mass and have potential for better transport properties [5], their reduced bandgap by increasing Ge content brings concern for some CMOS applications. This results in increased gate-induced drain leakage and high off current due to increased band-to-band or trap-assisted tunneling [6]. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging resulting in significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short channel on-state current at the target off-current at a scaled VDD. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain [7, 8] where the effective mass is significantly lowered and higher hole velocities can be achieved [5]. Therefore, the strain state in a scaled fin fabricated from biaxially strained substrates is pure uniaxial with optimal benefit for hole transport. The combination of uniaxial strain with great electrostatic integrity due to the non-planar device architecture as well as more manufacturing-friendly process, makes the moderate Ge content (such x=0.2-0.3) SiGe a very promising candidate for future generation of FinFETs. In order to evaluate the performance of s-SiGe FinFETs, SGOI substrates were fabricated using Ge condensation technique. This process is SOI CMOS compatible, where SiGe can be locally condensed in the pFET region while Si can be used for nFET or other on-chip applications. A final Ge fraction of x = 27.5% was measured by XRD, with minimal strain relaxation consistent with SIMS results (Figure 1(a)). The defectivity of SGOI substrates was measured using ex-situ Si capping followed by SECCO etch and dislocation density of ~ 1e4 cm-2 was measured for an optimized epitaxy and Ge condensation process. A gate first process flow was developed to fabricate our SiGe pMOS FinFETs [9]. As s-SiGe reactive-ion-etch resistance is much less than that of Si, the spacer RIE process was optimized to minimize fin recess in S/D regions and thus minimize stress relaxation. Raised S/D regions were formed using an ion-implant-free process by in-situ Boron-doped (ISBD) Si1-yGey (y > 40%) epitaxy with high Boron concentration, and dopant drive-in under the spacer to form the extensions. SGOI fins with vertical sidewalls and widths as scaled as 10nm demonstrated. Figure 1(b) shows typical XTEM of s-SiGe PMOS FinFET with sub-20nm physical gate length.Typical transfer and output characteristics of single-fin SiGe-channel PFETs (Fig. 2) exhibit excellent electrostatics with DIBL~50mV/V and SS ~90 mV/decade. In spite of high REXT ~ 0.4kΩ.μm, ION = 1.1 mA/µm was obtained at IOFF = 100 nA/µm and VDD = 1V. This high on current is attributed to the high source injection velocity exceeding 1e7 cm/s which is higher than SOI FinFETs with no stressors [10], and also higher than state-of the art bulk FinFETs [11]. Moreover, the SiGe PMOS FinFETs offers low off-state leakage suitable for high-performance and low-power applications. These criteria are hard to meet using state of the art Ge pFETs due to the significantly smaller bandgap [12]. In addition, unlike state of the art Ge pFETs, using a metal gate with a mid-gap work-function, target Vth has been achieved. In conclusion, we have demonstrated that s-SiGe channel FinFETs are a promising pFET candidate for future generations of high-performance devices and have a more manufacturable friendly process, than high-Ge content SiGe or Ge.REFERENCES[1] W. Haensch, IBM J. Res. & Dev., 2006. [2] S. Krishnan, IEDM 2011. [3] C. Ortolland, IEDM 2013. [4] A. Khakifirooz, IEEE TED 2009. [5] L. Gomez, IEEE TED, 2009. [6] C. Ni Chleirigh, IEEE TED, 2008. [7] T. Irisawa, IEDM 2005. [8] P. Hashemi, APL 2007. [9] P. Hashemi, VLSI 2013. [10] T. Yamashita, VLSI 2011. [11] C. Auth, VLSI 2012. [12] B. Duriez, IEDM 2013.

Invited; Ge-on-Insulator MOSFETs for High-Performance and 3D-LSI Applications

Germanium is recognized as new channel material to be introduced in near future CMOS technologies. The advantages are the high hole mobility, the high p-type dopant activation and the low contact resistivity, whereas the smaller band gap results in higher off state current than Si devices. Therefore, Ge-MOSFETs are considered to be most promising to use as a pMOS counterpart of III-V nMOSFETs for high-performance CMOS devices. In order to suppress the off leakage current, Ge-on-insulator (GeOI) substrates may be preferable than bulk substrates. On the other hand, the low thermal budget of the fabrication processes can provide another opportunity for Ge devices. Sequentially stackable COMS devices may be a possible application for 3D-LSIs instead of a TSV technology. Poly-Ge CMOS devices on insulating layers may be one of solutions for the 3D-LSIs. In this paper, electrical properties and processes of high performance strained Ge nanowire pMOSFETs and poly-Ge trigate pFETs both on buried oxide (SiO2) layers, which are dedicated for the former and the latter applications, respectively, are presented.The Ge nanowire devices were formed by a two-step Ge condensation technique for the channels and a self-aligned NiGe process for the source and drain [1]. A compressive strain of around 4% along the channel direction of <110> was observed after the condensation process, suggesting that no relaxation of the misfit strain between Si and Ge was occurred. A significantly high-hole mobility of 1922 cm2/Vs has been achieved thanks to the high strain and the good interfacial quality between the gate insulator and the Ge channel. Ion/Ioff over 105 has also been attained for the Ge nanowire pMOSFET with a gate length (Lg ) of 45 nm. Poly-Ge junction-less (JL) pFETs with a Lg down to 40 nm were formed on a SiO2 layer on a Si substrate [2]. The poly-Ge channel was naturally p-type with a hole concentration around 5x1018 cm-3 presumably due to the crystalline defects. No additional doping has been done. A high Ion/Ioff of around 105 was observed for narrow fin (7 nm) devices, although wider devices (>11 nm) exhibited degraded cut-off characteristics. We also found that the current drivability was drastically improved by using a flash lamp annealing (FLA) method due to the high hole mobility in the poly-Ge channel. A drain current value of 280 μA/μm was achieved at Vd =-1 V for the Lg =80 nm device [3], which is comparable with that of a mono-crystalline Si-pMOSFET of 130-nm technology node.In summary, two types of GeOI pMOSFETs for near-future high-performance logic CMOS-ICs and low-cost stackable applications were demonstrated. In both types of devices, the GeOI platform and non-planar gate configurations are key technologies to achieve sufficiently high Ion/Ioff values, which is one of major concerns to implement Ge devices into markets. Acknowledgement This work was granted by JSPS through FIRST Program initiated by the Council for Science and Technology Policy (CSTP).

Keynote; Material Challenges and Opportunities in Ge/III-V Channel MOSFETs

CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future. There can be several CMOS structures using III-V/Ge channels. One of the ultimate CMOS can be the co-integration of a III-V nMOSFET and a Ge pMOSFET. While Ge or III-V CMOS is also plausible in terms of the simplicity of the material integration, the key issues are the realization of high performance Ge nMOSFETs or III-V pMOSFETs. Also, even in Ge pMOSFETs and III-V nMOSFETs, the CMOS technologies have not been established yet. Thus, viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies.In addition, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of short channel effects by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks. Our approach for the channel formation is the wafer bonding for III-V materials and the Ge condensation technique for Ge/SiGe channels. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeOx-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT. We have proposed and demonstrated UTB InGaAs-based channel formation for III-V nMOSFETs by using direct wafer bonding. Ultrathin body (3.2 nm InGaAs)/UTBOX (Al2O3(4.4 nm)/SiO2(3.3 nm)) substrates are realized with high material quality. As channel engineering to boost the mobility in UTB InGaAs-based channels, we have introduced two boosters, higher In content InAs channels and MOS interface buffers composed of lower-In-content buffers. Based on these technologies, we have realized sub-20-nm-channel-length Tri-gate InGaAs/InAs/InGaAs-OI QW MOSFETs with good electrostatic. Here, wide-range Vth tunability in Tri-gate InAs-OI MOSFETs through VB control has been demonstrated. As for III-V pMOSFETs, we have also demonstrated UTB GaSb-OI pMOSFETs on Si by using wafer bonding. Based on these technologies, a novel III-V CMOS structure composed of GaSb/InAs hetero-structures is proposed.One of the most critical issues in Ge MOSFETs is the realization of gates stacks with superior MOS interfaces. In order to realize low Dit, high mobility and thin EOT at the same time, we have proposed a interfacial layer formation process employing ECR oxygen plasma to form GeOx ILs after thin Al2O3 or HfO2/Al2O3 ALD. This ultrathin GeOx IL is found to effectively reduce Dit in both valence and conduction band sides. N- and p-MOSFETs with the HfO2/Al2O3/GeOx/Ge gate stacks exhibit the excellent electrical characteristics under EOT of 0.76 nm. In spite of this ultrathin EOT, high electron and hole mobility is obtained in comparison with the thick GeO2/Ge mobility and the Si mobility, particularly in high Ns region. These results strongly demonstrate that HfO2/Al2O3/GeOx/Ge gate stacks can realize high performance Ge n- and pMOSFETs with minimal mobility expense under aggressive scaling of EOT.

(Invited) Strained Germanium Nanowire MOSFET with Low-Parasitic Resistance Metal Source/Drain

Introduction High mobility channel materials are extensively investigated to replace strained-Si in MOSFET devices to reduce power consumption by lowering supply voltages, V dd, without degrading circuit performance. Among the various high mobility channel materials, strained-Ge[1-4] is recognized as the most promising option for p-channel FETs due to its significantly high hole-mobility and compatibility with Si-CMOS process. This paper presents metal S/D nanowire pFETs having a high-mobility strained Ge channel formed by doping-free processes for channels and S/D. The large compressive strain as high as -3.9% resulted in a record high hole mobility (μ eff = 1992 cm2/Vs @ N s = 1.7x1012 cm-2) and a low contact resistivity (ρ c ~ 3.8x10-8 Ω cm2). Device fabrication Uniaxially strained-Ge nanowire channel was formed by the two-step Ge condensation technique, which induced uniaxial stress along the channel direction. As a gate insulator, GeOx interlayer and 3.2 nm- Al2O3 were grown by using MMT-plasma[4,5] and ALD, respectively. NiGe-metal S/D structures were formed by SALICIDE-like process on the unintentionally doped Ge nanowire. Detailed device fabrication process was shown in [3,4]. Figure 1(a) shows a XTEM of the narrowest channel with a wire width (W wire) of 15 nm. The Relationship between the W wire and strain applied to the channel was measured by a Raman spectroscopy. The dependence of strain along the channel direction ε xx on W wire is shown in Fig. 1(b). Extremely high (over -3.9%) strain, which is almost identical with the misfit strain between Ge and Si, was evaluated for sub W wire=40 nm devices. Device characterization Hole mobility was extracted by a split CV method for long-channel and multi-wire devices. Figure 2(a) shows hole-mobility of the fabricated multi-wire MOSFETs. The W wire = 40nm device, which has 95% Ge channel, showed a peak hole mobility of 1922 cm2/Vs at N s = 1.7x1012cm-2, which exceeds that of -3.8% strained-Ge nanowire MOSFET with Al2O3 gate stack[3]. Moreover, the obtained mobility at N s = 5x1012cm-2 is corresponding to 5.8 times of the counterpart of a state-of-the-art strained-Si pMOSFETs[1]. Ion / Ioff ~ 105 has also been attained for the strained-Ge nanowire pMOSFET with a gate length (Lg ) of 40 nm (Fig. 2(b)). A metal S/D MOSFET is an attractive candidate because of its low extension sheet resistance properties without a heavy doping in extension regions. However, parasitic resistance (R para) which is dominated by contact resistance (R c) between the extension metal and the inversion layer in this device, have been still an issue because of the decreasing contact area. Here, we demonstrate low R c characteristic due to low Schottky barrier height (SBH) for NiGe/ strained-Ge interface. The W wire dependence of parasitic resistance (R SD) were evaluated as shown in Fig. 3. Reduced R SD as low as 490 Ωμm for W wire = 54 nm device is achieved by using undoped Ge nanowire formed by two-step Ge condensation. The specific contact resistivity, ρ c of NiGe / strained-Ge interface was estimated by using previously proposed model[3]. Extremely low ρ c, that is as low as ~ 3.8x10-8 Ω cm2 has been achieved in spite of doping-free Schottky contact presumably due to the strong Fermi-level pinning to the valence band edge of the strained-Ge and reduction of SBH at Ni(Si)Ge/(Si)Ge interface by rising valence subband top energy for higher Ge concentration and strain. Conclusion Record high hole mobility (μ eff = 1922 cm2/Vs) and extremely low S/D contact resistivity (ρ c ~ 3.8x10-8 Ω cm2) were achieved for the highly strained-Ge nanowire pMOSFET. These results indicate that strained-Ge channels have a potential to serve as pFET channel of ultimately-scaled future CMOS.

Doppler Broadening Spectroscopy of Positron Annihilation near Ge and Si (001) Single Crystal Surfaces

carrier mobility compared with Si. 1 Although closely related to Si, in some aspects Ge shows a quite different behavior. This should be taken into account when processing steps are developed for the production of electronic devices with active Ge layers, in which the Ge layer surfaces and interfaces will play an important role. 2 In this letter, we investigated the effect of the free (001) surface on positron annihilation spectroscopy (PAS) results, comparing Si and Ge substrates. PAS is a powerful tool for the study of vacancy-type defects in semiconductors, 3,4 e.g. in irradiated Si and Ge. Positron trapping at vacancies can be observed by the narrowing of the Doppler-broadened 511 keV annihilation γ-ray peak. By varying the incident positron energy, one can probe different sample depths in the submicron range. This method is called Doppler Broadening Spectroscopy (DBS). The so called S-parameter, extracted from DBS, corresponds to positron annihilation by the valence electrons and is sensitive to open volume defects. An increase of the S-parameter can be simply interpreted as an increase of the number of vacancy-type defects. The S-parameter obtained for an incident positron energy lower than 2 keV, however, in general differs from the one obtained for positron energies above 15 keV. Incident positrons with lower energy will indeed mainly interact with the near surface area of the sample, and will be sensitive for thin native oxide layers, surface contamination, surface roughness, surface defects, etc. The S-parameter decreases in general toward the surface for most materials due to positron diffusion toward and annihilation at the surface. 5 The present letter reports on the different behavior of Si and Ge with this respect. While in case of Si, the S-parameter decreases considerably near the Si (001) surface as expected and as is the case for other semiconductor materials, in the case of a Ge (001) surface, the S-parameter shows no remarkable dependence on depth although both are group IV elements and have the same diamond structure. For the PAS measurements, moderately doped p-type Si and n-type Ge (001) wafers were used with a resistivity at room temperature in the range of 10–100 ohm corresponding with a carrier concentration at room temperature in the range of 10 13 ∼10 15 cm −3 . As a reference for the Si bulk and at the same time the near surface of Ge, a Geon-Insulator (GOI) wafer with a un-doped Ge top-layer produced by the Ge condensation technique, was also included in the study. The carrier concentration in the n-type Ge film of the GOI wafer that

Influence of SiGe layer thickness and Ge fraction on compressive strain and hole mobility in a SiGe-on-insulator substrate fabricated by the Ge condensation technique

Both compressive strain (εc) and hole mobility (μh) were investigated for SiGe-on-insulator substrates with different values for the SiGe layer thickness (d) and Ge fraction (Ge%), which were fabricated by Ge condensation. We found that the εc introduced during Ge condensation was strongly dependent on d and Ge%. Thinner d is helpful for maintaining higher εc when Ge% is 50%. εc is dramatically relaxed with a further increase in Ge%. By varying the tradeoff between Ge% and εc, we achieved a maximum μh of approximately 570cm2/V·s in the d range of 9–11nm and Ge% range of 50–65%.