GDSII File Research Articles

Designing Silicon Interposers for 2.5/3DIC Heterogeneous Integration - Meeting Foundry and OSAT Requirements

End market demand for higher performance, higher bandwidth and higher throughput processing such as AI, HPC, VR, 5G and even autonomous vehicles is driving the trend of heterogenous integration of ASICs, chiplets and memory, including HBM, onto advanced high-performance substrates using 2.5 and 3D IC assembly techniques that are manufactured using silicon or silicon-like processes. There are multiple suppliers of such advanced high-performance substrates ranging from the one stop mega foundries to multiple OSATs of different sizes. It’s fair to say that all of them have common design requirements or constraints that must pass a rigorous verification process of the manufacturing mask files (GDSII or OASIS). Such GDSII or OASIS files are post processed or exported from the physical design tools making the need to create the mask files with 100% fidelity an additional challenge to the design team. In this paper we will cover the major steps needed to design and implement an advanced silicon-based interposer that addresses common requirements of foundries and OSATs. We will talk about what each step is, why its required, any challenges that exist in addressing the step and actual design examples for each step. The major steps we will cover include: * What information you need from your manufacturer? * Definition of connectivity & floorplanning of the interposer * Defining the interposer materials stackup & vias for routing * Breakout or fanout routing from chiplet or IC pads * Power and ground mesh creation * Routing of interposer connectivity * Generation of interposer manufacturing data (GDS/OASIS) * Verification of the design to meet foundry/OSATs rules * Handoff to foundry/OSAT At the end of this paper attendees will understand what the major workflow steps for interposer design are and why. What general information they will need to obtain from their manufacturer in order to start design and how to use it. They will learn what each design step entails with clear examples which will enable creation of workflows to successfully handoff their designs to their chosen foundry or OSAT manufacturer.

Physical Design of 64-bit Multiplier and Accumulator (MAC) Unit Using Vedic Multiplier and CLA Adder

In digital signal processing, communication systems and many other applications, multiplier and accumulator units play a crucial role. This work presents an overview of 64-bit MAC Unit, where Vedic multiplier is used as multiplier unit and compared Carry select adders (CSA) and Carry look-ahead adder (CLA) which must be used for adder unit, accumulator unit consist of Parallel in parallel out (PIPO) shift registers. As a result, CLA adder to be more effective in terms of lower delay by comparing with other adders. The MAC Unit was modelled using Verilog-HDL, where its functional verification and synthesized was done using Intel Quartus Prime 21.1, which was simulated on Questa Intel FPGA 21.1. Further GDSII file was created using the cadence tool with the help of Incisive for functional simulation, Genus for synthesis and pre-layout timing analysis, and innovus for physical design. Entire study was carried out in 180nm technology from RTL-GDSII. The delay, power, area was monitored, the memory usage, Pre-Clock Tree Synthesis, Post-Clock Tree Synthesis (CTS) were noted before and after optimization of design.

Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives

Unintentional uncontrollable variations in the manufacturing process of integrated circuits are used to realize silicon primitives known as physical unclonable functions (PUFs). These primitives are used to create unique signatures for security purposes. Investigating the vulnerabilities of PUFs is of utmost importance to uphold their usefulness in secure applications. One such investigation includes exploring the susceptibility of PUFs to modeling attacks that aim at extracting the PUFs’ behavior. To date, these attacks have mainly focused on a single PUF instance where the targeted PUF is attacked using the model built based on the very same PUF’s challenge–response pairs or power side channel. In this article, we move one step forward and introduce <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cross-PUF</i> attacks where a model is created using the power consumption of one PUF instance to attack another PUF created from the same GDSII file. Through SPICE simulations, we show that these attacks are highly effective in modeling PUF behaviors even in the presence of noise and mismatches in temperature and aging of the PUF used for modeling versus the targeted PUF. To mitigate the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cross-PUF</i> attacks, we then propose a lightweight countermeasure based on dual-rail and random initialization logic approaches called DRILL. We show that DRILL is highly effective in thwarting <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Cross-PUF</i> attacks.

Hierarchical Design of a Secure Image Sensor with Dynamic Reconfiguration

This paper presents a secure reconfigurable hierarchical hardware architecture at the pixel and region level for smart image sensors to accelerate machine vision applications. The design maintains hierarchical processing that begins at the pixel level. It aims to reduce the computational burden on the sequential processor and increases the confidentiality of the sensor. We achieve this goal by preprocessing the data in parallel with event-based processing within the sensor and extract the local features, which are then forwarded to an encryption module. After that, an external processor can obtain the encrypted features to complete the vision application. This approach significantly accelerates the vision application by executing the low-level and mid-level image processing applications and simultaneously by reducing the data volume at the sensor level. The secure hardware architecture enables the vision application to perform in real-time with reliability. This hierarchical processing breaks the traditional sequential image processing and introduces parallelism for machine vision applications. We evaluate the design in FPGA and achieve the GDSII file in the ASIC platform at 800MHz. Simulation results show that the area overhead and power penalty for adding reconfiguration features stay in an acceptable range. Besides, removing redundant information, 84.01%, and 94.31% dynamic power can be saved at each pixel-level and region-level, respectively.

A Decomposition Workflow for Integrated Circuit Verification and Validation

This paper reviews a developed integrated circuit (IC) decomposition workflow that can be leveraged for extracting design files and performing advanced verification and validation techniques on fabricated chips. In this work, a commercial 130-nm microcontroller is delayered and imaged to recreate the full design stack-up. Using MicroNet’s Pix2Net, the features for each layer are extracted allowing a GDSII file to be generated and design netlists for target components to be recovered. The full decomposition process is executed on both the read only memory (ROM) array and universal serial communications interface (USCI) of the microcontroller to recover the layout GDSII and circuit netlist. A single-precision floating point unit (FPU) test article is used to incorporate a spectrum of error types into the design layout, thus creating a set of test articles with obfuscated errors. Once the netlists for each of the modified designs are extracted, formal verification techniques are applied to each netlist, thus illuminating the errors originally inserted into the layout. The extracted netlists are then converted into register transfer level (RTL) representations and simulated with the original design verification testbench.

Detecting Different Concentrations of Potassium Chloride Using the Sensor with Photonic Crystal in Nano Range

Sensitivity scheme with sensing and evaluating chemicals have been clued-up by means of photonic sensors by coalescing chemical constituents with their optophysical properties. In this article we have corroborated a 2D ring resonator using photonic crystal optical sensor which can detect potassium chloride by knowing the transmitted flux. According to the corresponding analogy peaks were explored. Yee’s method has been used for the assessment. Electromagnetic 2D model implemented to do the initiation all pass ring resonator photonic crystal. The different concentrations of potassium chloride respectively shifts its values with the respected frequency used in the design. The quality factor from the sensor is found to be 347663 and the sensitivity included is found to be in the range of 1.2 NM. The distinction in the minor level of the refractive index occur the alteration for the cause in the judicious forming the frequency that is obtained by observing the simulation. These technique that is used to authorize the design which is unequivocally an active sensors. This analogy of the paper was been made using the deliberated IPKISSIMEC tool. The GDSII file was generated with the OWL VISION tool and substantiated meticulously using the tool K-Layout . The ASCII code was formed using the generated OWLVISION tool.

Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering

A high degree of automation is required when facing full-IC reverse engineering. In this paper, we present a methodology to delayer the chip, acquire SEM images of each layer, obtain the three-dimensional layer reconstruction, and generate a vectorized file in GDSII format for further automatic netlist extraction. A custom software tool named GDS-X has been developed to perform all the required steps from image acquisition to the GDSII file generation. Applying a novel tile mosaicking strategy and using state-of-the-art machine learning techniques for image segmentation, this software reduces dramatically the time required to complete these procedures while minimizing errors compared to old manual reverse engineering techniques.

Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

Single-event effects (SEEs) have been the primary concern in study of radiation effects since late 1970s with the discovery of soft errors in terrestrial and space environments. The interaction of a single ionized particle with electronic devices leads to SEEs. In this paper, single-event upset (SEU) on CMOS devices in designing of a voltage-controlled oscillator (VCO) is analysed. Further, mitigation approaches of SEU are also discussed. To observe the impact of radiation, a VCO was designed in Cadence Virtuoso, and GDSII file of one ring oscillator stage was extracted to incorporate the same design in Silvaco MaskViews. With the help of layer map information file, masks were identified and used to design the CMOS inverter structure file for simulation of SEU condition. The input parameters for SEU simulation were evaluated from linear energy transfer (LET) graph of heavy ion under space conditions. The current profile of CMOS inverter was extracted under influence of a high-energy particle with the help of LET graph of that particle. This current profile was applied to different nodes of VCO and upset conditions were identified. Further, the impact of upset conditions on lock stage of phase-locked loop (PLL) is discussed. Results show that the SEU has significant impact on the logic state of inverters used in ring oscillator stage compared with current starving/biasing stage. The current profile of CMOS device has strong dependence on the energy of ion, its track, angle of incidence and the material. When angle of incidence is very less (\(7^{\circ }-14^{\circ }\)) the channel will be occupied by a funnel of charge and it leads to the maximum degradation of device. This work shows that a device operating at high frequency is more susceptible to SEU. Triple modular redundancy (TMR) and Radiation Hardened By Design (RHBD) can be used to mitigate SEU. TMR consumes more power and is less accurate compared with the RHBD approach.

Cache Controller for 4-way Set-Associative Cache Memory

This paper presents design of a cache controller for 4-way set associative cache memory and analyzing the performance in terms of cache hit verses miss rates. An FSM based cache controller has been designed for a 4-way set-associative cache memory of 1K byte with block size of 16 bytes. Main memory of 4K byte has been considered. The synthesis has been performed using Xilinx Synthesis Tool (XST) with Virtex-6 FPGA device XC6VLX240T. ISim simulator is used for functional verification of the designed code.The maximum output required time i.e. hold-time after clock is 0.777ns and minimum input time before clock arrival i.e. setup-time for designed module is 1.66ns. The maximum clock frequency is 257.202MHz.The design has also been synthesized in Cadence RTL Compiler tool. Finally, ASIC implementation of the designed cache controller has been done in Cadence Encounter Digital Implementation tool and the GDSII file has been generated.The designed cache controller consumes 5.53mW of total power.

Application of optical proximity correction technology

As process technology scales down to very deep sub-micron (VDSM) in semiconductor manufacturing technology, intrinsic size becomes close to or even shorter than the wavelength used for optical lithography. Thus, some distortions and deformations are introduced by optical proximity effects (OPE) mainly caused by the diffraction and interference of exposure light when layout patterns on a mask are transcribed to a wafer, which influence on the yield and performance of IC circuit. In order to compensate for the deformations, optical proximity correction (OPC) is the most commonly used methodology. Presently, the OPC method is to use a unitary toleration on the whole chip layer, which makes the run time of OPC algorithm longer, causes the size of GDSII files to follow exponential growth, and results in the cost of making mask grow immensely. Firstly, this paper proposes a self-adaptation OPC method with preprocessing function of patterns classification. According to the need of the correction precision, the OPC system divides patterns corrected into two groups with different toleration: critical patterns and general patterns, which enhance the efficiency of the OPC approach. Secondly, a model-based OPC method is presented based on pattern subsection and classification, which keeps the precision of the correction as well as enhances the efficiency. We also propose a rule-based OPC method with general, concise and complete correction rules, and achieve automatic-built rules-based and its looking-up. Thirdly, we also implement an OPC system, called MR-OPC; the MR-OPC system integrates both rule-based OPC and model-based OPC into a whole, so it can solve the confliction between the efficiency and precision. Experimental results show that the MR-OPC system we suggested has advantages of the efficiency and expansibility.