Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering

Abstract

A high degree of automation is required when facing full-IC reverse engineering. In this paper, we present a methodology to delayer the chip, acquire SEM images of each layer, obtain the three-dimensional layer reconstruction, and generate a vectorized file in GDSII format for further automatic netlist extraction. A custom software tool named GDS-X has been developed to perform all the required steps from image acquisition to the GDSII file generation. Applying a novel tile mosaicking strategy and using state-of-the-art machine learning techniques for image segmentation, this software reduces dramatically the time required to complete these procedures while minimizing errors compared to old manual reverse engineering techniques.